US 5,550,396 AGranted

Vertical field effect transistor with a trench structure

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorKazuhito Tsutsumi

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Abstract

A polycrystalline silicon film which is to be a channel is in a trench provided in a main surface of a silicon substrate. A gate insulating film is on the periphery of a polycrystalline silicon film. A gate electrode is on the periphery of the gate insulating film. A silicon oxide film is on the periphery of the gate electrode. A source/drain film is on the periphery of the silicon oxide film. A silicon oxide film is on the periphery of the source/drain film. A source/drain film is electrically connected to the polycrystalline silicon film. A source/drain film is electrically connected to the polycrystalline silicon film. Since the polycrystalline silicon film extends along the depth direction of trench, a channel length can be sufficient to prevent a short channel effect. Also, compared to the case in which an epitaxial layer is used as a channel, since the polycrystalline silicon film is used as a channel, the time required for manufacturing the device can be shortened.

Claims21

Dependent claims

A field effect transistor formed in a hole portion provided in a main surface of a semiconductor substrate, comprising:

a first polycrystalline silicon film, which is to be a channel, located in said hole portion, extending along the depth direction in said hole portion, and including a first end portion on the side of said main surface and a second end portion on the side of a bottom of said hole portion;
a gate electrode located in said hole portion,
extending along the depth direction of said hole portion and facing said first polycrystalline silicon film with a gate insulating film interposed therebetween;
a first source/drain film located on the periphery of said first polycrystalline silicon film and said gate electrode in said hole portion, extending along the depth direction of said hole portion, and electrically connected to said second end portion;
a first insulating film located in said hole portion and electrically insulating said first source/drain film from said gate electrode;
a second insulating film located in said hole portion and electrically insulating said first source/drain film from said semiconductor substrate;
a second source/drain film located above said main surface and electrically connected to said first end portion wherein said first source/drain film and said gate electrode extend above said main surface;
and
said first source/drain film is electrically connected to a source/drain region of another field effect transistor formed in said main surface, and
said gate electrode is electrically connected to a gate electrode of said another field effect transistor,
wherein the electrode of said another field effect transistor further comprises a portion of the gate electrode of said field effect transistor extending above said main surface.

8 more elements

A semiconductor device comprising:

a field effect transistor formed in a hole portion provided in a main surface of a semiconductor substrate, comprising;
a first polycrystalline silicon film of a first conductivity type, which is to be a channel, located in said hole portion, extending along the depth direction in said hole portion, and including a first end portion on the side of said main surface and a second end portion on the side of a bottom of said hole portion;
a gate electrode located in said hole portion, extending along the depth direction of said hole portion and facing said first polycrystalline silicon film with a gate insulating film interposed therebetween;
a second polycrystalline silicon film of a second conductivity type different and formed separately from said first polycrystalline silicon film, which is to be a first source/drain, located on the periphery of said first polycrystalline silicon film and said gate electrode in said hole portion, extending along the depth direction of said hole portion, and electrically connected to said second end portion;
a first insulating film located in said hole portion and electrically insulating said first source/drain film from said gate electrode;
a second insulating film located in said hole portion and electrically insulating said first source/drain film from said semiconductor substrate;
a third polycrystalline silicon film of a second conductivity type different and formed separately from said first polycrystalline silicon film, which is to be a second source/drain, located above said main surface and electrically connected to said first end portion.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/449,611Filed 24 May 1995 · continuation
Priority: JP 4-01141224 Jan 1992
Granted: 27 Aug 1996
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 30/0321
Of thin-film transistors [TFT]: comprising silicon, e.g. amorphous silicon or polysilicon
H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10D 30/0318
Of thin-film transistors [TFT]: of vertical TFTs
H10D 30/6728
Thin-film transistors [TFT]: vertical TFTs