US 5,548,150 AGranted

Field effect transistor

AssigneeKabushiki Kaisha Toshiba

InventorsIchiro Omura, Akio Nakagawa, Tadashi Sakai, Masayuki Sekimura, Hideyuki Funaki

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Abstract

A high-resistant p-silicon layer is formed on a silicon substrate through a silicon oxide film. N-source and n-drain layers are selectively formed in the surface of the high-resistant p-silicon layer. A gate electrode is formed through a gate insulating film on a channel region between the source and drain layers. To induce an n-inverted layer under the gate electrode, a p-base layer is formed in the high-resistant p-silicon layer. A depletion layer extending from a pn junction between the n-drain layer and the high-resistant p-silicon layer reaches the silicon oxide film in a thermal equilibrium state. Part of the high-resistant p-silicon layer extends into a channel region between the drain and base layers. The drain and base layers are connected to each other through part of the depletion layer in the thermal equilibrium state. A field effect transistor having a high-speed operation is provided.

Claims20

Dependent claims

A high-frequency MOS field effect transistor comprising:

a substrate comprising a first layer of an insulator material and a second layer of a semiconductor material;
an active layer of said semiconductor material formed on a surface of said first layer;
a source layer of a first conductivity type formed on a surface of said active layer and extending to said first layer;
a source electrode connected to said source layer;
a drain layer of the first conductivity type formed in said active layer and extending from said active layer surface to said first layer and not in contact with said source layer;
a drain electrode connected to said drain layer;
a base layer of a second conductivity type formed in said active layer extending from said surface of said active layer to said first layer so as to induce an inverted layer of the first conductivity type between said source and drain layers;
a gate insulating film formed on said base layer;
a gate electrode formed on a surface of said gate insulating film over said base layer;
a short-circuiting layer formed in said active layer surface adjacent to said source layer to interconnect said base layer and said source electrode;
a connecting member of an electrically and thermally conductive material extending through said first layer to electrically and thermally connect said source electrode to said second layer;
and
means for grounding said second layer.

10 more elements

A field effect transistor comprising:

a substrate;
an active layer arranged on said substrate and essentially consisting of a semiconductor material;
first and second base layers of a second conductivity type formed in a surface of said active layer so as to be in contact with each other, said first base layer having an electrical resistance higher than that of said second base layer and being arranged on said substrate;
a source layer of a first conductivity type formed in a surface of said second base layer;
a source electrode connected to said source layer;
a drain layer of the first conductivity type formed in a surface of said first base layer;
a drain electrode connected to said drain layer;
and
a gate electrode facing said second base layer through a gate insulating film for inducing an inverted layer of the first conductivity type in said second base layer between said source and drain layers,
wherein a depth, W, and an impurity concentration, N, of said first base layer between said drain layer and said substrate are such that a depletion layer formed in said first base layer extends from a junction between said drain and first base layers to said substrate in a thermal equilibrium state when a voltage, V, applied between said source and drain electrodes is zero volts and thus also in an operation state when said inverted layer is formed.

7 more elements

A field effect transistor comprising:

a substrate,
an active layer arranged on said substrate and essentially consisting of silicon;
first and second base layers of a second conductivity type formed in a surface of said active layer in contact with each other, said first base layer having an electrical resistance higher than that of said second base layer and arranged on said substrate;
a source layer of a first conductivity type formed in a surface of said second base layer;
a source electrode connected to said source layer;
a drain layer of the first conductivity type formed in a surface of said first base layer;
a drain electrode connected to said drain layer;
and
a gate electrode facing said second base layer through a gate insulating film for inducing an inverted layer of the first conductivity type in said second base layer between said source and drain layers,
wherein a depth, W, and an impurity concentration, N, of said first base layer between said drain layer and said substrate are determined such that a depletion layer formed in said first base layer extends from a junction between said drain and first base layers to said substrate in a thermal equilibrium state when a voltage, V, applied between said source and drain electrodes is zero volts and thus also in an operation state when said inverted layer is formed.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/425,246Filed 17 Apr 1995 · continuation
Priority: JP 5-04953710 Mar 1993
Granted: 20 Aug 1996
Term ends: Not estimatedThe source records don’t support an estimate.

Classification28 codes

H10D 30/657
Lateral dmos [ldmos] fets: having substrates comprising insulating layers, e.g. SOI-LDMOS transistors
H01F 41/046
Printed circuit coils: structurally combined with ferromagnetic material
H10D 12/411
Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]: insulated-gate bipolar transistors [IGBT]
H10D 18/251
Thyristors: lateral thyristors