Personalizable gate array devices
AssigneeQuick Technologies Ltd.
InventorZvi Orbach
Life of this patent
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Abstract
Customizable semiconductor/devices, integrated circuit gate arrays and techniques to produce same are disclosed. The devices comprise integrated circuit blanks having a collection of semiconductor elements and at least one metal layer including fusible links interconnecting said collection of semiconductor elements into an inoperably connected integrated circuit blank. At least one metal layer is first etched thereby to define a pattern of conductors. A passivation layer is provided over at least one metal layer, afterwhich at least one metal layer is etched a second time for selectably removing the fusible links, thereby converting the inoperable integrated circuit blank into a selected operable electronic function.
Claims15
A CMOS gate array device comprising:
- a substrate,
- a collection of individual semiconductor elements formed on the substrate, and
- a plurality of links interconnecting the collection of individual semiconductor elements into an inoperably connected CMOS gate array device, some of said plurality of links having designated fuse locations,
- said collection of semiconductor elements being interconnected for converting the inoperable CMOS gate array device into a selected operable electronic function upon disconnection of predetermined ones of plurality of links at said designated fuse locations.
A CMOS gate array device comprising:
- a substrate,
- a collection of transistors mounted on the substrate having input/output pins for operating the CMOS gate array device and,
- a plurality of links connecting the transistors into an inoperable circuit device, said plurality of links having designated fuse locations and being without electrical fusing connections capable of fusing the links at said fuse locations by electrical current supplied through the input/output pins of the circuit, said collection of transistors being interconnected for converting the inoperable circuit device into an operable circuit device upon disconnecting of predetermined ones of said plurality of links at ones of said designated fuse locations.
Dependencies are inferred from the claim text.