US 5,545,586 AGranted

Method of making a transistor having easily controllable impurity profile

AssigneeNEC Corporation

InventorRisho Koh

Life of this patent

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Abstract

On the substrate of an integrated circuit chip is deposited a first insulating layer in which a low resistivity semiconductor region is subsequently formed. An insulating film is formed on a side wall of the low resistivity semiconductor region. A slit is formed in the first insulating layer so that a portion of the substrate and a portion of the insulating film are exposed. First, second and third semiconductor layers of different conductivity types are epitaxially grown in the slit so that the second layer is in contact with the exposed insulating film. A second insulating layer is deposited on the chip. Through the second insulating layer first, second and third electrodes are brought into contact with the first and third semiconductor layers and with the low resistivity semiconductor region. Due to the stacking of epitaxial layers of different conductivity types, the impurity profiles of the epitaxial layers can be precisely controlled.

Claims4

Dependent claims

A method of fabricating a transistor, comprising the steps of:

providing a substrate of a first conductivity type;
forming a first insulating layer on the substrate;
forming a conductive region on the first insulating layer;
forming a second insulating layer on the conductive region:
successively removing portions of the second insulating layer, said conductive region and said first insulating layer and forming an opening extending to the substrate, and forming a sidewall of the conductive region;
forming a sidewall insulator on the sidewall of the conductive region;
forming a region of easily removable material on a sidewall of said opening, said easily removable region being adjacent said first insulating layer, said sidewall insulator and said second insulating layer and leaving a portion of said opening exposed;
filling the exposed portion of said opening with an insulating material;
removing the easily removable region and forming a slit;
and
forming a semiconductor region within the opening, the semiconductor region having a first portion of a second conductivity the opposite to the first conductivity type, the first portion being adjacent the first insulating layer, the semiconductor region having a second portion of the first conductivity type, the second portion being adjacent the sidewall insulator and overlying the first portion, and the semiconductor region having a third portion of the second conductivity type, the third portion being adjacent the second insulating layer and overlying the second portion.

8 more elements

A method of fabricating a transistor, comprising the steps of:

providing a substrate of a first conductivity type;
forming a first insulating layer on the substrate;
forming a conductive region on the first insulating layer;
forming a second insulating layer on the conductive region;
successively removing portions of the second insulating layer, said conductive region and said first insulating layer and forming an opening extending to the substrate;
removing a sidewall portion of the conductive region and forming a recessed sidewall portion of the conductive region;
forming a sidewall insulator in said recessed portion of the conductive region;
forming a region of easily removable material on a sidewall of said opening, said easily removable region being adjacent said first insulating layer, said sidewall insulator and said second insulating layer and leaving a portion of said opening exposed;
filling the exposed portion of said opening with an insulating material;
removing the easily removable region and forming a slit;
and
forming a semiconductor region within the slit, the semiconductor region having a first portion of a second conductivity type opposite to the first conductivity type, the first portion being adjacent the first insulating layer, the semiconductor region having a second portion of the first conductivity type, the second portion being adjacent the sidewall insulator and overlying the first portion, and the semiconductor region having a third portion of the second conductivity type, the third portion being adjacent the second insulating layer and overlying the second portion.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/242,147Filed 13 May 1994 · division
Priority: JP 2-32479927 Nov 1990
Granted: 13 Aug 1996
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10D 62/151
Source or drain regions of field-effect devices: of igfets
B82Y 10/00
Nanotechnology for information processing, storage or transmission
H10D 30/014
Manufacture or treatment: of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron…
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]