Fine resolution digital delay line with coarse and fine adjustment stages
AssigneeTexas Instruments Incorporated
InventorsJoseph A. Casasanta, Bernhard H. Andresen, Yoshinori Satoh, Stanley C. Keeney, Robert C. Martin
Life of this patent
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Abstract
A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.
Claims32
A digital phase locked loop circuit, comprising:
- a phase detector for detecting a phase relationship between first and second clock signals, said phase detector having first and second input for said first and second clock signals to be applied thereto;
- first means connected to said phase detector for providing delay adjustment of a first range;
- second means responsive to said phase detector and to said first means for providing delay adjustment of a second range, a combination of said first and second means providing a precise delay adjustment;
- and
- said phase detector including a control circuit which, at a point in time when an edge of said second clock signal trails a corresponding edge of said first clock signal by less than one-half cycle, outputs a first control signal to said first and second means to cause the length of delay of said precise delay adjustment to increase until said edge of said second clock signal is eventually time-shifted past the next successive corresponding edge of said first clock signal.
A digital delay line for inserting propagation delay into a signal path, comprising:
- a first delay circuit for providing delay adjustment of a first range, said first delay circuit comprising at least one input receiving a clock signal, said first delay circuit comprising a synchronous divide by circuit;
- an element circuit;
- a halfstep switching logic circuit coupling said synchronous divide by circuit to said element circuit, each of said circuits having at least one input connected to an input of said first delay circuit and at least one output connected to an output of said first delay circuit;
- and
- a second delay circuit responsive to said first delay circuit, said second delay circuit providing delay adjustment of a second range.
A digital delay line for inserting propagation delay into a signal path, comprising:
- a first delay circuit for providing delay adjustment of a first range, said first delay circuit comprising a synchronous divide by circuit, a halfstep switching logic circuit, and an element circuit;
- a first input of said synchronous divide by circuit coupled to receive a clock signal, a second input of said synchronous divide by circuit coupled to receive a clear signal;
- a first input of said halfstep switching logic circuit connected to a first output of said synchronous divide by circuit and to a first output of said first delay circuit a second input connected to a second output of said synchronous divide by circuit and to a second output of said first delay circuit a third input coupled to receive said clear signal, and a first output connected to a third output of said first delay circuit a first input of said element circuit connected to a data input of said first delay circuit, a second input connected to a second output of said halfstep switching logic and to a fourth output of said first delay circuit and an output connected to a fifth output of said first delay circuit;
- and
- a second delay circuit responsive to said first delay circuit, said second delay circuit providing delay adjustment of a second range.
A method for synchronizing a pair of periodic digital waveforms each including a series of alternately rising and falling pulse edges, comprising the steps of:
- propagating a first periodic digital waveform through a delay path comprising a first delay circuit having stages for delay adjustment of a first range and a second delay circuit, responsive to said first delay circuit, having stages for delay adjustment of a second range, said delay path having an adjustable propagation delay;
- obtaining a second periodic digital waveform at an output of the delay path;
- and
- increasing the propagation delay of the delay path even when an edge of the second waveform trails a corresponding edge of the first waveform by less than one-half cycle, including the step of continuing to increase the propagation delay of the delay path until said edge of the second waveform is eventually time-shifted past the next successive corresponding edge of the first waveform.
Dependencies are inferred from the claim text.