Optimization circuitry and control for a synchronous memory device with programmable latency period

A memory device having a memory array of rows and columns of memory cells, said memory device operating in synchronization with a system clock, said device comprising:

• a row address latch coupled to address terminals and latching a row address upon receiving a row latching signal;
• a column address latch coupled to said address terminals for latching a column address;
• an optimization circuit receiving a latency signal and a column latching signal, said optimization circuit adjusts said column latching signal to produce an adjusted column latching signal;
• a column address buffer latch coupled to said column address latch, said column address buffer latch produces said column address for column address decoding in response to said adjusted column latching signal;
• and
• memory access circuitry coupled to said memory array for accessing a portion of said memory array designated by said row address and said column address.

A method for optimizing memory access time in a memory device having a memory array of rows and columns of memory cells and operating in synchronization with a system clock, said method comprising the steps of:

• providing said memory device with a latency period;
• latching a column address;
• providing a column latching signal;
• adjusting said column latching signal if a latency signal indicates a predetermined latency period;
• and
• providing said column address for column address decoding in response to said adjusted column latching signal.

A synchronous dynamic random access memory having a memory array of rows and columns of memory cells, said memory comprising:

• a row address latch coupled to address terminals and latching a row address upon receiving a row latching signal;
• a column address latch coupled to said address terminals for latching a column address;
• a latency delay circuit receiving a latency signal and a column latching signal, said latency delay circuit delays said column latching signal to produce an adjusted column latching signal;
• a column address buffer latch coupled to said column address latch, said column address buffer latch produces said column address for column address decoding in response to said adjusted column latching signal;
• and
• memory access circuitry coupled to said memory array for accessing a portion of said memory array designated by said row address and said column address.

A method for optimizing memory access time in a random access memory device having a memory array of rows and columns of memory cells and operating in synchronization with a system clock, said method comprising the steps of:

• providing said memory device with a latency period;
• latching a column address;
• providing a column latching signal;
• delaying said column latching signal by a predetermined amount if a latency signal indicates a predetermined latency period;
• and
• providing said column address for column address decoding in response to said adjusted column latching signal.