US 5,544,071 AGranted

Critical path prediction for design of circuits

AssigneeIntel Corporation

InventorsDoron Keren, Igal Izsak, Iaacov Kobrinsky

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Abstract

An automatic method of critical path prediction in a computer system used with a network model representative of a circuit. Gate delays are determined for each cell used for each of the drivers in the combinational block. Load delays are also determined for each cell used for each of the drivers in the combinational block. Estimated delays may then be determined for each path between each of the drivers in the combinational block and sinks coupled to each of the drivers in the combinational blocks. Static timing analysis on the combinational block is performed by using the gate delays, the load delays, and the estimated delays to determine estimated required times and total capacity for each primary output of the sinks of the combinational block, and to determine estimated arrival times for each primary input of the drivers of the combinational block.

In a computer system, an automatic method of critical path prediction in a network model representative of a circuit, comprising performing the following steps for each combinational block in said network model:

a. determining gate delays for each cell used for each of the drivers in said combinational block by:
(i) if said cell comprises an AND logical function and a number of outputs of the cell is less than or equal to a Fanin cone for said cell, then computing said gate delay for said cell using an average internal delay for said cell and a capacitance of said cell;
(ii) if said cell comprises an AND logical function and said number of outputs of said cell exceeds said Fanin cone for said cell then computing said gate delay for said cell using a weighted length of a path from an input to an output of said cell using said average internal delay for said cell and said capacitance of said cell;
(iii) if said cell comprises an OR logical function and said number of outputs of said cell is less than or equal to said Fanin cone for said cell then computing the gate delay for said cell using the length of the path from an input to an output of said cell;
and
(iv) if said cell comprises an OR logical function and said number of outputs of said cell exceeds said Fanin cone for said cell then computing said gate delay for said cell using said weighted length of a path from an input to an output of said cell using said average internal delay for said cell and said capacitance of said cell;
b. determining load delays for each cell used for each of said drivers in said combinational block;
c. determining estimated delays for each path between each of said drivers in said combinational block and sinks coupled to each of said drivers in said combinational blocks;
and
d. performing a static timing analysis on said combinational block by using said gate delays, said load delays, and said estimated delays to determine estimated required times and total capacitance for each primary output of said sinks of said combinational block, and to determine estimated arrival times for each primary input of said drivers of said combinational block.

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Abstract

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