US 5,542,059 A · Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order

Abstract

A CPU pipeline is able to process instructions from a complex instruction set computer CISC instruction set and from a reduced instruction set computer RISC set. A mode register is provided to indicate whether RISC or CISC instructions are currently being processed. Two instruction decode units are used, one for each instruction set. Compound CISC instructions flow from the decode pipestage to the address generate stage, then to an operand cache stage, and finally to an algebraic execute stage before the results are written back to the GPR register. When the CPU switches to RISC mode by clearing a mode bit in the mode register, the pipeline is re-arranged for processing the simpler RISC instructions. Two outputs are provided for the RISC instruction decoder. The first output is for simple execute-type instructions, while the second output is for load/store-type instructions, and connects to the address generate pipestage, which generates an address for the operand cache stage. These instructions are prevented from continuing to the execute stage by a mux. The mux normally connects the operand cache stage to the execute stage when CISC instructions are being processed, but the mux directly connects the second output of the RISC instruction decoder to the execute stage when the mode register enables RISC instruction decoding. This reduces the latency for RISC instructions by 1 or 2 clocks. An alternate embodiment re-arranges the pipeline dynamically as simple instructions are detected by the decode units. The preferred embodiment uses a fixed pipeline with the execute hardware relocatable to the D, C, or M pipestages. Thus the pipeline is optimized for both RISC and CISC instructions.

Claims16

Dependent claims

A CPU having a pipeline for processing a plurality of instructions from two separate instruction sets, said pipeline comprising:

first instruction decode means for decoding instructions from said first instruction set, said first decode means providing decoded instructions to said plurality of functional units, said first instruction set having a first encoding of opcodes to instructions;
second instruction decode means for decoding instructions from said second instruction set, said second instruction set having a second encoding of opcodes to instructions, said second encoding of opcodes to instructions being separate and independent from said first encoding of optodes to instructions, said second decode means providing decoded instructions to said plurality of functional units;
enable means for enabling either said first instruction decode means or said second instruction decode means, said enable means coupled to said first instruction decode means and coupled to said second instruction decode means;
a plurality of functional units for processing said plurality of instructions;
a relocatable functional unit in said plurality of functional units, said relocatable functional unit for executing native instructions from both of said two separate instruction sets;
means for indicating which one of said two separate instruction sets is being processed by said plurality of functional units;
and
means for relocating, responsive to said indicating means, said relocating means for temporally relocating said relocatable functional unit in time and sequence order to other functional units in said plurality of functional units.

5 more elements

Dependencies are inferred from the claim text.

Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order

Life of this patent

Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order

Life of this patent

Abstract

Claims16