Arithmetic-free digital interpolation filter architecture

A digital interpolation filter for filtering a digital input signal at a first sampling frequency comprised of a sequence of digital values and providing a filtered digital output for each of the digital values, comprising:

• a random access memory having a plurality of storage locations for storing the digital values of the digital input signal, each of said storage locations randomly addressable by an external address for output from said random access memory;
• a first memory device for storing a plurality of sequences of filter coefficients as filter coefficient sequences, each of said filter coefficient sequences associated with one of the digital outputs and each comprising the filter coefficients of a finite impulse response (FIR) filter function necessary to calculate the associated digital output;
• a second memory device for storing a plurality of sequences of addresses for said random access memory as address sequences, each of said address sequences associated with one of said filter coefficient sequences in said first memory device and each of said addresses in each of said address sequences being associated with the corresponding one of said filter coefficients in the corresponding one of said filter coefficient sequences in said first memory device;
• an arithmetic device for multiplying the addressed output of said random access memory with the value represented by the output of said first memory device;
• an accumulator for accumulating the output of said arithmetic device;
• and
• a control device for controlling said second memory device to sequence through the addresses in each of said address sequences in a sequential manner for addressing of said random access memory and to sequentially output from said random access memory the associated one of said stored samples to said arithmetic device, said control device controlling said first memory device to output to said arithmetic device the one of said filter coefficients corresponding to the output one of said addresses from said second memory device, the output of said accumulator at the end of each of said sequences comprising the digital output for the associated input digital value.

A processor for processing a time series of digital values, which digital values are in a predetermined sequence, comprising:

• an input associated with each of the digital values;
• an output associated with each of the digital values to provide a processed output digital value;
• a data memory for storing the input digital values;
• a coefficient memory for storing a plurality of processing coefficients;
• an input selection network for accessing select ones of said stored digital inputs;
• a processor element for processing each of said stored digital inputs to provide an associated output in accordance with a predetermined algorithm, said predetermined algorithm requiring as data inputs a plurality of said stored input digital values including said associated digital value, and as coefficient inputs, a plurality of said stored processing coefficients, said data inputs selected by said input selection network, said predetermined algorithm having an arithmetic operation associated with each of said data inputs, with each of said arithmetic operations requiring an associated one of said input processing coefficients to provide a plurality of processed output values for each of said associated digital values;
• and
• an accumulator for summing said processed output values for each of said outputs to provide said associated processed output digital value for each of the input digital values;
• a processor controller for controlling the processing sequence in which said arithmetic operations are performed for each of said outputs and controlling said input selection network to select the appropriate one of said data inputs, wherein said processing sequence can be different than the sequence in which said associated data inputs occur in the predetermined sequence of the digital values.

A digital filter for filtering a digital input signal at a sampling frequency comprised of a sequence of digital input values and providing a digital filter output signal comprised of a plurality of digital outputs, one for each of the digital input values, comprising:

• a first memory device for storing a portion of the sequence of digital input values;
• a second memory device for storing filter coefficients associated with a Finite Impulse Response (FIR) filter function, said filter coefficients restricted to only discrete values, each of the digital outputs requiring a predetermined number of arithmetic operations to be performed between predetermined ones of the digital input values and predetermined ones of said filter coefficients stored in said second memory device;
• a processor clock operating at a higher frequency than the sampling frequency;
• an arithmetic processor for performing for each of the digital outputs each of said associated arithmetic operations, each of the arithmetic operations requiring a predetermined number of clock cycles of said processor clock with the total number of clock cycles for all of said arithmetic operation for each of the digital outputs being less than or equal to a single sampling period associated with the sampling frequency;
• and
• an accumulator for accumulating the results of all of said arithmetic operations performed by said operational device for each of the digital outputs and outputting the resulting digital output after accumulation of all of said associated performed arithmetic operations.

A method for filtering a digital output signal at a sampling frequency is comprised of a sequence of digital input values and providing a digital filter output signal comprised of a plurality of digital outputs, one for each of the digital input values, comprising the steps of:

• storing a portion of the sequence of the digital input values in a first memory device;
• storing filter coefficients associated with a finite impulse response (FIR) filter function in a second memory device, the filter coefficients restricted to only discrete values, each of the digital outputs requiring a predetermined number of arithmetic operations to be performed between predetermined ones of the digital input values and predetermined ones of the filter coefficients stored in the second memory device, of which at least one of the arithmetic operations for each of the digital outputs results in a zero value;
• performing for each of the digital outputs each of the associated arithmetic operations with the exception of the at least one arithmetic operation;
• and
• accumulating the results of all the arithmetic operations performed by the step of performing for each of the digital outputs and outputting the resulting digital output after accumulation of all of the associated performed arithmetic operations.

A method for filtering a digital input signal at a sampling frequency comprised of a sequence of digital values and providing a filtered digital output for each of the digital values, comprising the steps of:

• providing a random access memory having a plurality of storage locations and storing the digital values of the digital input signals in the storage locations, each of the storage locations randomly addressable by an external address for output from the random access memory;
• storing a plurality of sequences of filter coefficients in a first memory device as filter coefficient sequences, each of the filter coefficient sequences associated with one of the digital outputs and each comprising the filter coefficient of a finite impulse response (FIR) filter function necessary to calculate the associated digital output;
• storing a plurality of sequences of addresses for the random access memory as address sequences in a second memory device, each of the address sequences associated with one of the filter coefficient sequences in the first memory device and each of the addresses in each of the address sequences being associated with the corresponding ones of the filter coefficients in the corresponding ones of the filter coefficient sequences in the first memory device;
• multiplying the addressed output of the random access memory with a value represented by the output of the first memory device in an arithmetic device;
• accumulating the output of the arithmetic device in an accumulator;
• and
• controlling the second memory device to sequence through the addresses in each of the address sequences in a sequential manner for addressing of the random access memory and to sequentially output from the random access memory and to sequentially output from the random access memory the associated one of the stored samples to the arithmetic device, the step of controlling the first memory device operable to control the first memory device to output to the arithmetic device the one of the filter coefficients corresponding to the output one of the addresses from the second memory device, the output of the accumulator at the end of each of the sequences comprising the digital output for the associated input value.

A method for processing a time series of digital values, which digital values are in a predetermined sequence, comprising the steps of:

• inputting each of the digital values on a separate input associated with each of the digital values;
• providing an output associated with each of the digital values to provide a processed output digital value;
• storing the input digital values in the data memory;
• storing a plurality of processing coefficients in a coefficient memory;
• accessing select ones of the stored digital inputs with an input selection network;
• processing each of the stored digital inputs to provide an associated output in accordance with a predetermined algorithm, the predetermined algorithm requiring as data inputs a plurality of the stored input digital values including the associated digital value and, as coefficient inputs, a plurality of the stored processing coefficients, the data input selected by the data input selection network, the predetermined algorithm having an arithmetic operation associated with each of the data inputs, with each of the arithmetic operations requiring an associated one of the input processing coefficients to provide a plurality of processed output values for each of the associated digital values;
• and
• summing the processed output values in an accumulator for each of the outputs to provide the associated processed output digital value for each of the input digital values;
• and
• controlling the processing sequence in which the arithmetic operations are performed in the step of processing and controlling the input selection network to select the appropriate one of the data inputs, wherein the processing sequence can be different than the sequence in which the associated data inputs occur in the predetermined sequence of digital values.