Back to results
US 5,541,538 AGranted
High speed comparator
AssigneeHarris Corporation
InventorsKantilal Bacrania, Gregory J. Fisher
Life of this patent
Estimating the term…
Abstract
A comparator 10 has a first stage differential amplifier 11 coupled to a second stage, single ended differential amplifier 12. The output of the second stage is coupled to a latch input stage 15 of a latch 16. A latch replica bias circuit 20 operates the second stage at a clamp voltage corresponding to the threshold voltage of latch 16. A clock signal clk switches the second stage 12 between gain and clamp modes.
Claims17
A comparator comprising:
- a two-stage differential amplifier having first and second stages,
- said first stage having one input for receiving an input signal and another input for receiving a reference voltage and a first stage output for providing a first stage output signal representative of the difference between the input signal and the reference voltage;
- said second stage having a differential amplifier switchable between gain and clamp modes and having a second stage input coupled to the first stage output of the first stage, a bias input and a second stage output for providing a second stage output signal representative of the second stage input signal, wherein the second stage output is set to a clamp level voltage during the clamp mode;
- means for switching the second stage between a gain mode and a clamped mode;
- and
- a latch input stage having an input coupled to the second stage output, said latch input stage having a threshold level voltage and having a latch output for providing a latch output signal representative of whether the latch input is greater than or less than the threshold level voltage of the latch, wherein the clamp level voltage is the same as the threshold level voltage.
3 more elements
A comparator comprising:
- an amplifier having gain and clamp modes comprising a differential input for receiving a differential input signal, a differential pair of transistors coupled to the input, a bias input for providing a bias current to the differential pair and an amplifier output providing an output signal representative of the differential input signal, wherein the amplifier output is set to a clamp level during the clamp mode;
- means for switching the amplifier between the gain mode and the clamp mode;
- and
- a latch input stage having an input coupled to the output of said differential pair, said latch input stage having a threshold level and having a latch output for providing a latch output signal representative of whether a latch input signal is greater than or less than the threshold level of the latch, wherein the latch is the replica of a bias circuit coupled to the bias input which generates the bias current and wherein the clamp level corresponds to the threshold level of the latch.
1 more element
An analog to digital converter comprising:
- an input for receiving an analog signal;
- a plurality of comparators coupled to the input signal for comparing the analog signal to a plurality of signals of different levels for converting the analog signal into a digital signal representative of the magnitude of the analog signal, each of said comparator comprising
- a two-stage differential amplifier having first and second stages,
- said first stage having a first stage input for receiving a first stage input signal corresponding to a predetermined portion of said analog input signal and a first stage output for providing a first stage output signal representative of the first stage input signal;
- said second stage having a differential amplifier having gain and clamped modes, a second stage input coupled to the first stage output of the first stage, a bias input and a second stage output for providing a second stage output signal representative of the second stage input signal, wherein the second stage output is set to a clamp voltage during the clamped mode;
- means for switching the second stage between said gain and clamped modes;
- and
- a latch input stage having an input coupled to the second stage output, said latch input stage having a threshold voltage and having a latch output for providing a latch output signal representative of whether the latch input is greater than or less than the threshold voltage of the latch.
5 more elements
A method for comparing an input signal to a reference signal and latching the results of such comparison comprising the steps of:
- comparing the input signal to the reference signal;
- generating an output signal proportional to the difference between the input signal and the reference signal;
- latching the output signal when the output signal exceeds a threshold level;
- and
- clamping the output signal at the threshold level.
2 more elements
Dependencies are inferred from the claim text.