US 5,541,530 AGranted

Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks

AssigneeAltera Corporation

InventorsRichard G. Cliff, Cameron McClintock, William Leong

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Abstract

A programmable logic array integrated circuit device has logic regions grouped in blocks, which are in turn grouped in super-blocks. The super-blocks are disposed on the device in a two-dimensional array of intersecting rows and columns. Global conductors are associated with each row and column. Super-block feeding conductors associated with each super-block feed signals from the global conductors to any logic region in the super-block. Local feedback conductors feed back logic region output signals to all logic regions in a block. The super-block feeding conductors are also used to interconnect the logic regions in a super-block so that the global conductors do not have to be used for that purpose.

Claims14

Dependent claims

A programmable logic array integrated circuit device comprising:

a plurality of logic regions, each of which has a plurality of input terminals and at least one output terminal, and each of which is programmable to produce at its output terminal an output logic signal which is any of a plurality of logic functions of input logic signals applied to its input terminals, said logic regions being grouped in a plurality of blocks such that each of said blocks includes a respective sub-plurality of adjacent ones of said logic regions, said blocks being grouped in a plurality of super-blocks such that each of said super-blocks includes a respective sub-plurality of adjacent ones of said blocks, said super-blocks being disposed on said integrated circuit in a two-dimensional array of intersecting rows and columns of said super-blocks;
a plurality of row conductors associated with each of said rows, each of said row conductors extending along the length of the associated row;
a plurality of column conductors associated with each of said columns, each of said column conductors extending along the length of the associated column;
a plurality of super-block feeding conductors associated with each of said super-blocks, each of said super-block feeding conductors extending adjacent the logic regions of the associates super-block;
a plurality of local feedback conductors associated with each of said blocks, each of said local feedback conductors extending adjacent the logic regions of the associated block and being connected to the output terminal of a respective one of the logic regions of the associated block;
a plurality of inter-block conductors associated with each of said super-blocks, each of said inter-block conductors being connected to the output terminal of a respective one of the logic regions of the associated super-block;
a first programmable logic connector array associated with each of said pluralities of super-block feeding conductors for selectively connecting said super-block feeding conductors to row conductors associated with the row which includes the super-block associated with said super-block feeding conductors;
a second programmable logic connector array associated with each of said super-blocks for selectively connecting said super-block feeding conductors to inter-block conductors which are associated with said super-block;
a third programmable logic connector array associated with each of said logic regions for selectively connecting the input terminals of said logic region to local feedback conductors associated with the block which includes said logic region and to super-block feeding conductors associated with the super-block which includes said logic region;
and
a fourth programmable logic connector array associated with each of said super-blocks for selectively connecting the inter-block conductors associated with said super-block to row and column conductors respectively associated with the row and column which include said super-block.

8 more elements

A programmable logic array integrated circuit device comprising:

a plurality of logic regions, each of which has a plurality of input terminals and at least one output terminal, and each of which is programmable to produce at its output terminal an output logic signal which is any of a plurality of logic functions of input logic signals applied to its input terminals, said logic regions being grouped in a plurality of blocks such that each of said blocks includes a respective sub-plurality of adjacent ones of said logic regions, said blocks being grouped in a plurality of super-blocks such that each of said super-blocks includes a respective sub-plurality of adjacent ones of said blocks, said super-blocks being disposed on said integrated circuit in a two-dimensional array of intersecting rows and columns of said super-blocks;
a plurality of row conductors associated with each of said rows, each of said row conductors extending along the length of the associated row;
a plurality of column conductors associated with each of said columns, each of said column conductors extending along the length of the associated column;
a plurality of super-block feeding conductors associated with each of said super-blocks, each of said super-block feeding conductors extending adjacent the logic regions of the associates super-block;
a plurality of inter-block conductors associated with each of said super-blocks, each of said inter-block conductors being connected to the output terminal of a respective one of the logic regions of the associated super-block;
a first programmable logic connector array associated with each of said pluralities of super-block feeding conductors for selectively connecting said super-block feeding conductors to row conductors associated with the row which includes the super-block associated with said super-block feeding conductors;
a second programmable logic connector array associated with each of said super-blocks for selectively connecting said super-block feeding conductors to inter-block conductors which are associated with said super-block;
a third programmable logic connector array associated with each of said logic regions for selectively connecting the input terminals of said logic region to super-block feeding conductors associated with the super-block which includes said logic region;
and
a fourth programmable logic connector array associated with each of said super-blocks for selectively connecting the inter-block conductors associated with said super-block to row and column conductors respectively associated with the row and column which include said super-block.

7 more elements

Dependencies are inferred from the claim text.