Transistorless, multistable current-mode memory cells and memory arrays and methods of reading and writing to the same

A circuit for storing information as one of at least two possible bistable current states comprising:

• a) at least a first cell comprising
• at least a first transistorless device exhibiting negative differential resistance;
• and
• at least a second transistorless device coupled to the first transistorless device;
• b) at least a first word line having a first voltage level, the first word line being coupled to the first cell;
• and
• c) at least a first bit line having a second voltage level, the first bit line being coupled to the first cell,
• wherein during a current-mode read operation, a logic stored in the first cell is read when the voltage of the first word line is raised by a predetermined amount, .delta., wherein the first cell coupled to the first word line produces, in the first bit line coupled to the first cell, a first cell read current,
• wherein during the current-mode read operation, a second cell coupled to the first word line and to a second bit line generates a second cell read current, but a third cell coupled to a second word line and to the first bit line generates a third cell standby current,
• wherein a first bit line read current is generated in the first bit line, and a second bit line read current is generated in the second bit line,
• wherein a first sense amplifier coupled to the first bit line senses the first bit line read current, and at the same time a second sense amplifier coupled to the second bit line senses the second bit line read current,
• wherein a voltage across the first cell and a voltage across the second cell increase by an amount equal to the voltage increase .delta. in the first word line, while a voltage across the third cell remains at a standby voltage level,
• wherein the first sense amplifier determines the first cell's logic state by detecting a change between the first bit line read current and a current generated in the first bit line during a standby mode, and the second sense amplifier determines the second cell's logic state by detecting a change between the second bit line read current and a current generated in the second bit line during the standby mode.

A circuit for storing information as one of at least two possible bistable current states comprising:

• a) at least a first cell comprising
• at least a first transistorless device exhibiting negative differential resistance;
• and
• at least a second transistorless device coupled to the first transistorless device;
• b) at least a first word line having a first voltage level, the first word line being coupled to the first cell;
• and
• c) at least a first bit line having a second voltage level, the first bit line being coupled to the first cell
• wherein during a current-mode read operation, a logic stored in the first cell is read when the voltage of the first word line is raised by a predetermined amount, .delta., wherein the first cell coupled to the first word line produces, in the first bit line coupled to the first cell, a first cell read current,
• wherein during the current-mode read operation, a second cell coupled to the first word line and to a second bit line generates a second cell read current, but a third cell coupled to a second word line and to the first bit line generates a third cell standby current,
• wherein a first bit line read current is generated in the first bit line, and a second bit line read current is generated in the second bit line,
• wherein a first sense amplifier coupled to the first bit line senses the first bit line read current, and at the same time a second sense amplifier coupled to the second bit line senses the second bit line read current,
• wherein a voltage across the first cell and a voltage across the second cell increase by an amount equal to the voltage increase .delta. in the first word line, while a voltage across the third cell remains at a standby voltage level,
• wherein the first sense amplifier determines the first cell's logic state by detecting the first bit line read current, and the second sense amplifier determines the second cell's logic state by detecting the second bit line read current.

A circuit for storing information as one of at least two possible bistable current states comprising:

• a) at least a first cell comprising
• at least a first transistorless device exhibiting negative differential resistance;
• and
• at least a second transistorless device coupled to the first transistorless device;
• b) at least a first word line having a first voltage level, the first word line being coupled to the first cell;
• and
• c) at least a first bit line having a second voltage level, the first bit line being coupled to the first cell
• wherein during a current-mode write operation, when the voltage of the first word line is raised by a predetermined amount, .DELTA., and the voltage of the first bit line is lowered by a predetermined amount, .PSI., a logic state 1 is written to the first cell by storing a corresponding current level in the first cell, the first cell being coupled to the first word line and to the first bit line,
• wherein a second cell that is coupled to the first word line and to a second bit line, a third cell that is coupled to the first bit line and to a second word line, and a fourth cell that is coupled to the second word line and to the second bit line maintain their previous logic states wherein a voltage across the first cell increases by an amount equal to the sum of the .DELTA. and the .PSI., a voltage across the second cell increases by an amount equal to the .DELTA., a voltage across the third cell increases by an amount equal to the .PSI., and a voltage across the fourth cell remains at a standby voltage level.

A circuit for storing information as one of at least two possible bistable current states comprising:

• a) at least a first cell comprising
• at least a first transistorless device exhibiting negative differential resistance;
• and
• at least a second transistorless device coupled to the first transistorless device;
• b) at least a first word line having a first voltage level, the first word line being coupled to the first cell;
• and
• c) at least a first bit line having a second voltage level, the first bit line being coupled to the first cell
• wherein when the voltage of the first word line is lowered by a predetermined amount, .DELTA., and the voltage of the first bit line is raised by a predetermined amount, .PSI., a logic state 0 is written to the first cell that is coupled to the first word line and to the first bit line,
• wherein a second cell that is coupled to the first word line and to a second bit line, a third cell that is coupled to the first bit line and to a second word line, and a fourth cell that is coupled to the second word line and the second bit line maintain their previous logic states wherein a voltage across the first cell decreases by an amount equal to the sum of the .DELTA. and the .PSI., a voltage across the second cell decreases by an amount equal to the .DELTA., a voltage across the third cell decreases by an amount equal to the .PSI., and a voltage across the fourth cell remains at a standby voltage level.