Multilevel converter with capacitor voltage balancing

A multilevel convertor for connection to a single-phase or multiphase AC system, the convertor comprising:

• a plurality of series-connected capacitors, the capacitors being arranged, when the convertor is switched on, to be charged to an initial DC voltage,
• a plurality of switch means for each phase for connecting each node of the plurality of capacitors in turn onto the AC system, said switch means having respective control inputs,
• a main control loop arrangement for controlling the timing of the coupling of each node of the plurality of capacitors in turn onto the AC system, the main control loop arrangement including, for each phase:
• a switching control means for performing switching operations on said switch means, said switching control means having a control input and a plurality of outputs connected to respective control inputs of said switch means,
• an error signal producing means for producing an error signal representative of a difference between an actual value of an electrical quantity to be controlled and a reference value of said quantity, an output of said error signal producing means being connected to said control input of said switching control means,
• a plurality of subsidiary control loops for each phase, said plurality of subsidiary control loops being one fewer in number than said plurality of capacitors and being associated with respective pairs of said capacitors, each subsidiary control loop including a first combining means having a first input for receiving a first signal proportional to a difference between mean DC voltage levels on a pair of capacitors associated with that subsidiary control loop, and a second input for receiving a second signal proportional to tap currents entering a pair of nodes associated with said pair of capacitors, the first combining means having an output which is taken to an input of said error signal producing means such that said output signal of said first combining means is additively combined with said error signal, said subsidiary control loops serving to maintain a predetermined relationship between the mean DC voltage levels on said plurality of capacitors.