Direct stacked and flip chip power semiconductor device structures

A stacked power semiconductor device configuration comprising:

• first and second power semiconductor device structures, each of said power semiconductor device structures comprising:
• a semiconductor chip having an active major surface and an opposite major surface, contact pads on the active major surface comprising one main terminal of the chip and a control terminal, and the opposite major surface comprising another main terminal of the chip;
• a thermally-conductive dielectric layer overlying at least portions of the active major surface, with vias formed in said dielectric layer in alignment with said contact pads,
• a patterned metallization layer over said thermally-conductive dielectric layer, portions of said patterned metallization layer extending through said vias into electrical contact with said contact pads, and
• a metal electrode structure bonded to selected areas of said patterned metallization so as to be electrically and thermally coupled thereto;
• and
• the opposite major surface of said semiconductor chip of said first power semiconductor device structure being bonded to the metal electrode structure of said second power semiconductor device structure so as to be electrically and thermally coupled thereto.

A power semiconductor device assembly comprising:

• a semiconductor chip having an active major surface and an opposite major surface, contact pads on the active major surface comprising one main terminal of the chip and a control terminal, and the opposite major surface comprising another main terminal of the chip;
• a thermally-conductive dielectric layer overlying at least portions of the active major surface, with vias formed in said dielectric layer in alignment with said contact pads;
• a patterned metallization layer over said thermally-conductive dielectric layer, portions of said patterned metallization layer extending through said vias into electrical contact with said contact pads;
• and
• a heat-dissipating device-mounting structure including metal pads bonded to selected areas of said patterned metallization layer so as to be electrically and thermally coupled thereto.