Data transmission/receive system and control method using dummy data to signify transmission/reception state and to detect transmission error
AssigneeSamsung Electronics Co., Ltd.
InventorDong Y. Nam
Life of this patent
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Abstract
An invertor room air-conditioner for transmitting/receiving data between indoor and outdoor microprocessors, in which one microprocessor is synchronized with the remaining microprocessor using its internal clock pulse, while the microprocessors perform the data transmission/reception using dummy data previously stored therein, respectively, thereby removing the data transmission/reception errors and the influence of the exterior noises.
Claims7
A system for data transmission/reception between microprocessors comprising:
- a first microprocessor including means for generating synchronizing clock signals from an inner timer;
- judging means for determining whether most significant bits of data received during a data receiving mode corresponds to dummy data previously stored in a table in said first microprocessor;
- means for identifying a transmission or a reception state of said first microprocessor based upon a value of said dummy data;
- and means for determining whether data transmission/reception has been effective responsive to the judging means determination of whether the received data corresponds to the dummy data which signify a transmission or a reception state;
- and
- a second microprocessor including judging means for determining whether the most significant bits of data received during a data receiving mode corresponds to dummy data previously stored in a table in said second microprocessor, and means for determining if data transmission/reception has been effective responsive to the judging means determination of whether the most significant bits of the received data corresponds to the dummy data which signify a transmission of a reception state.
A control method for data transmission/reception between microprocessors comprising the steps of:
- operating an inner timer of any one of the microprocessors to generate synchronizing clock signals for each of said microprocessors therefrom;
- forcing the microprocessors to output dummy data previously stored in a table therein in order to be operated in one of a receiving mode and a transmitting mode;
- judging whether most significant bits of any one of a plurality of received data groups received by any of the microprocessors in the receiving mode corresponds to the dummy data;
- determining whether data transmission/reception was effective responsive to whether the most significant bits of any one of the received data groups corresponds to the dummy data which signify a transmission or a reception state;
- and
- entering, in each of said microprocessors, either a data transmission mode or a data reception mode based upon a value of said dummy data.
A method for controlling data communication between a first and second processor comprising the steps of:
- establishing a table of dummy data values which are stored in each of said first and second processors, at least one of said dummy data values signifying a data transmission mode and at least one of said dummy data values signifying a data reception mode;
- transmitting first data, including said at least one of said dummy data values signifying said data transmission mode, from said first processor to said second processor;
- transmitting second data, including said at least one of said dummy data values signifying said data reception mode, from said second processor to said first processor;
- determining whether data transmission/reception was effective based on the dummy data values signifying the data transmission/reception mode;
- and
- operating on said first and second data based upon said respective dummy data values.
Dependencies are inferred from the claim text.