Apparatus, systems and methods for implementing memory embedded search arithmetic logic unit

An active memory constructed as a single device, said single device having a pin configuration compatible with a pin configuration of a selected inactive memory comprising:

• a data memory including an array of memory cells arranged as plurality of rows and columns for holding data bits;
• data memory control circuitry coupled to said data memory for selectively transferring data bits between said cells in said data memory and a first internal bus;
• a broadcast memory including an array of memory cells arranged as a plurality of rows and columns for holding control bits and instruction bits defining a search instruction set;
• broadcast memory control circuitry coupled to said broadcast memory for selectively transferring control and instruction bits between said cells in said broadcast memory and a second internal bus;
• a datapath coupled to said first and second internal buses, said datapath including search circuitry operable to receive words of data from said data memory and test said words against a search test condition selected from said search instruction set;
• and
• a controller coupled to said datapath, said broadcast memory control circuitry, and said data memory control circuitry, and operable in response to said control bits received from said broadcast memory to direct the transfer of said data bits to said datapath from said data memory, and the test of said data bits by said search circuitry.