Process for fabricating a semiconductor device having an improved metal interconnect structure
AssigneeMotorola, Inc.
InventorsLouis C. Parrillo, Jeffrey L. Klein
Life of this patent
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AssigneeMotorola, Inc.
InventorsLouis C. Parrillo, Jeffrey L. Klein
Estimating the term…
A metal interconnect structure includes copper interface layers (24, 30) located between a refractory metal via plug (28), and first and second metal interconnect layers (16, 32). The copper interface layers (24, 30) are confined to the area of a via opening (22) in an insulating layer (20) overlying the first interconnect layer (16) and containing the via plug (28). The interface layers (24, 30) are subjected to an anneal to provide copper reservoirs (36, 37) in the interconnect layers (16, 32) adjacent to the interface layers (24, 30). The copper reservoirs (36, 37) continuously replenish copper depleted from the interface when an electric current is passed through the interconnect structure. A process includes the selective deposition of copper onto an exposed region (23) of the first metal interconnect layer (16), and onto the upper portion the via plug (28), followed by an anneal in forming gas to form the copper reservoirs (36, 37).
A process for fabricating a semiconductor device comprising the steps of:
A process for fabricating a semiconductor device comprising the steps of:
A process for forming a semiconductor device comprising the steps of:
A process for fabricating a semiconductor device comprising the steps of:
A process for fabricating a semiconductor device comprising the steps of:
Dependencies are inferred from the claim text.