Burst EDO memory device

A memory device having an address strobe signal node for receiving an address strobe signal and an array of memory elements, the memory device comprising:

• an address latch responsive to a first transition of the address strobe signal to latch at least a portion of a first initial memory address into the memory device;
• an address generating circuit adapted to generate a series of burst addresses which are determinable from the first initial memory address, wherein each of the burst addresses is generated in response to a corresponding transition of the address strobe signal;
• and
• a control circuit in electrical communication with said address latch and the address strobe signal node for enabling said address latch to latch at least a portion of a second initial address into the memory device in response to the address strobe signal after a predetermined number of burst access cycles have occurred.

A memory device having a plurality of data nodes for receiving and driving a plurality of data signals, an array of memory elements, and a plurality of address nodes for receiving a row and a column address, the memory device comprising:

• a row address strobe node for receiving a row address strobe signal for latching the row address in the memory device;
• a write control signal node for receiving a write control signal for selecting between read and write accesses of the memory device;
• and
• first and second column address strobe nodes for receiving first and second column address strobe signals, wherein either of said first and second column address strobe signals latch the column address, and either of said first and second column address strobe signals being active during a read access of the memory device will enable data to be driven on each of the data nodes, and only a first plurality of the data signals will be stored in the array in response to said write control signal selecting a write access and said first column address strobe node being active and said second column address strobe node being inactive.

A memory device having an array of memory elements, in which a row address has been selected, comprising:

• a means of selecting a first column address and accessing an element of the array of memory elements at the row and first column address, in response to a transition of a column address strobe signal;
• and
• a means for modifying the first column address within the memory device to provide a second column address and for accessing a further element of the array, in response to the column address strobe signal;
• an output buffer to provide output data from the memory device only after a plurality of transitions of the column address strobe signal in a burst read access;
• and
• a control circuit responsive to a write enable signal to terminate a burst access of the memory device.

A method of reading data from a memory device having an address latch, an address counter, an address strobe node for receiving a column address strobe, an output data driver and an array of memory elements, the method comprising:

• applying a first column address strobe to the address strobe node for latching a first column address;
• accessing a first memory element of the array of memory elements at the first column address;
• applying a second column address strobe to the address strobe node for advancing the column address within the memory device to specify a second column address;
• accessing a second memory element of the array of memory elements at the second column address;
• switching data driven to an external data node from a logic low level to a logic high level in response to a single transition of the column address strobe;
• and
• maintaining a high impedance state on the output data driver at least until said step of applying the second column address strobe.

A Single In Line Memory Module comprising:

• a memory device having an array of memory elements, each of the memory elements having an associated address;
• a plurality of address lines coupled to said memory device;
• and
• an address strobe signal line electrically coupled to said memory device, wherein said memory device is responsive to an address strobe signal received on said address strobe signal line to latch an address within said memory device from said plurality of address lines, and said memory device is responsive to a transition of the address strobe signal received on said address strobe signal line to advance the address within said memory device in a predetermined sequence.

A Memory Module comprising:

• a memory device;
• a plurality of address signal lines coupled to said memory device to provide an address to said memory device;
• an address strobe signal line coupled to said memory device;
• and
• an address generation circuit within said memory device, coupled to said address strobe signal line, for receiving and advancing the address, to provide multiple data accesses of said memory device in synchronization with multiple transitions of an address strobe signal on said address strobe signal line after only one address is received.

A computer system comprising:

• a microprocessor that provides an address;
• and
• a memory device containing data at a location corresponding to the address, said memory providing burst access in response to the address, wherein burst access comprises:
• a plurality of periods, a column address strobe signal being received by said memory each period;
• a column address portion, of the address, being received by said memory device only in a first period of the plurality of periods in response to the column address strobe signal;
• and
• the data at the location corresponding to the address is provided at an output of said memory device after at least two periods.