Symmetric clock system for a data processing system including dynamically switchable frequency divider

A dynamically switchable frequency clock system for use in a data processing system, comprising:

• a frequency doubler circuit for doubling a frequency of an input signal to improve resulting of the clock system;
• a counter controlled by a divisor select signal, said counter having an input connected to an output of said frequency doubler circuit;
• first and second compare circuits, each having a first set of inputs connected to outputs of said counter and a second set of inputs connected to outputs from a divisor select circuit, said first compare circuit having an output connected to a counter reset gate and to a reset input of a clock out latch, said second compare circuit having an output connected to a set input of said clock out latch;
• and
• a latch for providing a dynamically selectable frequency clock signal in response to an input clock signal and a selected divisor.