Logic structure and circuit for fast carry

A multi-bit adder comprising:

• a first carry logic block, a second carry logic block, and a third carry logic block, each block including:
• a first input terminal;
• a second input terminal;
• a first carry in terminal;
• a second carry in terminal;
• a carry out terminal;
• a logic structure coupled to said first and second input terminals;
• a first structure for selectively providing a signal on said first input terminal to said carry out terminal;
• and
• a second structure for connecting either said first carry in terminal or said second carry in terminal,
• wherein said multi-bit adder further includes:
• a first line coupled to the first carry in terminal of said first carry logic block;
• a second line coupled to the carry out terminal of said second carry logic block;
• a third line coupled to the second carry in terminal of said third carry logic block;
• a fourth line;
• a first connection means for selectively connecting said first line and said fourth line;
• a second connection means for selectively connecting said second line and said fourth line;
• and
• a third connection means for selectively connecting said third line and said fourth line.

A carry logic device comprising:

• a first input line and a second input line, both lines receiving input signals;
• a first carry in line and a second carry in line, both carry in lines receiving carry in signals;
• a carry out line for providing carry out signals from said carry logic device;
• and
• circuitry for providing an internal signal, said circuitry being coupled to said first and second input lines, said first and second carry in lines, and said carry out line, wherein said circuitry selectively determines whether said first input line is coupled to said carry out line, or said first carry in line or said second carry in line is coupled to said carry out line.