Method and apparatus for improving the resolution of pulse position modulated communications between an implantable medical device and an external medical device

A timing generator for an implantable medical device, said timing generator producing a pulse in a pulse position modulated signal, wherein the position of said pulse is determined relative to an externally generated signal from an external medical device, comprising:

• a delay timer which receives at a first input terminal a signal indicative of a preset delay period, and which receives at a second input terminal a clock signal, said delay timer functioning to count for a period defined by the preset delay period, at a rate determined by the clock signal, and said delay timer providing an output signal indicative of the count of the delay timer;
• a phase timer capable of counting up and down at a constant rate, said phase timer including a first input terminal for receiving a fast clock signal, a second input terminal for receiving a signal indicating the direction in which said phase timer should count, and an output terminal for providing an output signal indicative of the phase timer count;
• logic circuitry coupled to said phase timer to provide a signal to said phase timer indicating the direction in which said phase timer counts;
• an oscillator providing the fast clock signal to said phase timer to indicate the rate at which said phase timer counts;
• and
• an output gate receiving the output signal from said delay timer and from said phase timer, said output gate providing the pulse in the pulse position modulated signal.

A timing generator for an implantable medical device, said timing generator producing a pulse for a pulse position modulated signal, wherein the position, of the pulse in the pulse position modulated signal is determined relative to an external signal generated by an external medical device, said timing generator comprising:

• a delay timer which receives a signal indicative of a preset delay period, and which also receives an internal clock signal, said delay timer functioning to count for a period defined by the preset delay period, at a rate defined by the internal clock signal, and providing an output signal indicative of the count of said delay timer;
• a capacitor for storing a voltage;
• a first current source selectively coupled to said capacitor for increasing the voltage on said capacitor at a constant rate;
• a second current source selectively coupled to said capacitor for decreasing the voltage of said capacitor at a constant rate;
• logic circuitry coupled to said delay timer, said logic circuitry selectively coupling one of said current sources to said capacitor;
• a voltage source providing a reference voltage;
• and
• a comparator for comparing the voltage on said capacitor with the reference voltage for determining a period for phase difference between the internal clock signal and said external signal.