US 5,522,058 AGranted

Distributed shared-memory multiprocessor system with reduced traffic on shared bus

AssigneeKabushiki Kaisha Toshiba

InventorsShigeaki Iwasa, Takashi Omizo

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Abstract

A distributed shared-memory multiprocessor system capable of reducing a traffic on the shared bus, without imposing any constraint concerning the types of variables to be accessed in the parallel programs, such that a high system extensibility can be realized. The system is formed by a plurality of processor units coupled through a shared bus, where each processor unit comprises: a CPU; a main memory connected with the CPU through an internal bus, for storing a distributed part of data entries of a shared-memory of the system; a cache memory associated with the CPU and connected with the main memory through the internal bus, for caching selected data entries of the shared-memory; and a sharing management unit connected with the main memory and the cache memory through the internal bus, For interfacing the internal bus and the shared bus according to a sharing state for each data entry of the main memory and a cache state of each data entry of the cache memory.

Claims2

Dependent claims

A distributed shared-memory multiprocessor system formed by a plurality of processor units coupled through a shared bus, each processor unit comprising:

central processing unit (CPU);
a main memory connected with the CPU through an internal bus, for storing a distributed part of data entries of a shared-memory of the system;
a cache memory associated with the CPU and connected with the main memory through the internal bus, for caching selected data entries of the shared-memory;
and
a sharing management unit connected with the main memory and the cache memory through the internal bus, for interfacing the internal bus and the shared bus, including:
cache state tag means for storing a cache state of each data entry of the cache memory indicative of whether said each data entry of the cache memory has been updated in the cache memory of said each processor unit and not written back to the shared-memory;
intervention means for intervening during an access to a certain data entry in a main memory of a different processor unit, in response to a read command received from said different processor unit through the shared bus, when cache state of said certain data entry in the cache state tag means indicates that said certain data entry has been updated in the cache memory of said each processor unit and not written back to the shared memory;
and
control means for controlling a cache state for said certain data entry in the cache state tag means to make a state transition from one cache state with an ownership for said certain data entry indicating presence of a duty to write back a newest value of said certain data entry from the cache memory to the main memory to another cache state without an ownership for said certain data entry indicating an absence of a duty to write back a newest value of said certain data entry from the cache memory to the main memory, when the intervention means intervenes during the access to said certain data entry in said main memory of said different processor unit, and a cache state for a particular data entry other than said certain data entry in the cache state tag means to make a state transition from one cache state without an ownership for said particular data entry indicating an absence of a duty to write back a newest value of said particular data entry from the cache memory to the main memory to another cache state with an ownership for said particular data entry indicating a presence of a duty to write back a newest value of said particular data entry from the cache memory to the main memory, when an access to said particular data entry from said each processor unit is intervened by an intervention means of another processor unit.

6 more elements

A shared-memory multiprocessor system formed by first and second processor units coupled through a shared bus, each processor unit comprising:

a central processing unit (CPU);
a main memory connected with the CPU through an internal bus, for storing a distributed part of data entries of shared-memory of the system;
a cache memory associated with the CPU and connected with the main memory through the internal bus, for caching data entries of the shared-memory;
and
a sharing management unit, including a cache state tag means, connected with the main memory and the cache memory through the internal bus, for interfacing with the internal bus and the shared bus,
wherein, during a read access by the second processor unit to a memory location in the main memory of the second processing unit but corresponding to a cache line that the cache state tag means in the first processing unit indicates that the first processor unit owns, the sharing management unit of the first processor unit revokes the ownership of the cache line from the first processor unit by making a state transition from one cache state with an ownership for said cache line indicating a presence of a duty to write back a newest value of said cache line from the cache memory of the fine first processor unit to the main memory of the first processor unit to another cache state without an ownership for said cache line indicating an absence of a duty to write back a newest value of said cache line from the cache memory of the first processor unit to the main memory of the first processor unit, and the sharing management unit of the second processor unit changes the second cache state tag means to indicate that the second processor unit owns the cache line by making a state transition from one cache state without an ownership for said cache line indicating an absence of a duty to write back a newest value of said cache line from the cache memory of the second processor unit to the main memory of the second processor unit to another cache state with an ownership for said cache line indicating a presence of a duty to write back a newest value of said cache line from the cache memory of the second processor unit to the main memory of the second processor unit.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/112,811Filed 11 Aug 1993
Priority: JP 4-21313311 Aug 1992
Granted: 28 May 1996
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 12/0813
Multiuser, multiprocessor or multiprocessing cache systems: with a network or matrix configuration
G06F 12/0826
Using directory methods: limited pointers directories; State-only directories without pointers
G06F 2212/2542
Distributed memory: non-uniform memory access [NUMA] architecture
G06F 2212/622
Details of cache specific to multiprocessor cache arrangements: state-only directory, i.e. not recording identity of sharing or owning nodes