Semiconductor memory device having a coincidence detection circuit and its test method
AssigneeNEC Corporation
InventorToru Ishikawa
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a plurality of memory blocks, a write circuit for writing data into the memory blocks, a read circuit for reading data from the memory blocks, a plurality of serial registers, each of which is connected to the corresponding memory block to output serially a plurality of data read from the memory block, a plurality of switches, each of which is arranged between two adjacent ones of the serial registers to connect the serial registers in series, and a coincidence detection circuit for detecting a coincidence of data outputted from a final serial register arranged at a final end of the serial registers connected by the switches with data outputted from a serial register arranged immediately before the final serial register.
Claims10
A semiconductor memory device comprising:
- a plurality of memory blocks;
- a write circuit for writing data into said memory blocks;
- a read circuit for reading data from said memory blocks;
- a plurality of serial registers, each of said serial registers being connected to a corresponding memory block to output serially a plurality of data read from the memory block;
- a plurality of switches, each of said switches being arranged between two adjacent ones of said serial registers to connect said serial registers in series;
- and
- coincidence detection means for detecting a coincidence of data outputted from a final serial register arranged at a final end of said serial registers connected by said switches with data outputted from a serial register arranged before said final serial register.
A semiconductor memory device comprising:
- a plurality of memory blocks (=n blocks);
- a plurality of n serial registers, each of said serial registers being connected to a corresponding memory block to output serially a plurality of data read from the memory block;
- a plurality of switches for connecting said n serial registers by every m serial registers in series;
- and
- a plurality of coincidence detection circuits, wherein each of said coincidence detection circuits is arranged to detect a coincidence of data outputted from a final serial register of the m serial registers connected by the switches with data outputted from a serial register arranged immediately before the final serial register.
A method for testing a semiconductor memory, wherein said semiconductor memory device comprises a plurality of memory blocks, a write circuit for writing data into said memory blocks, a read circuit for reading data from said memory blocks, a plurality of n serial registers, each of said n serial registers being connected to a corresponding memory block to output serially data read from the memory block, the method comprising steps of:
- writing same data in said memory blocks at a test;
- inputting data read from said memory blocks to said serial registers;
- shifting the data in said n serial registers sequentially;
- and
- monitoring a result of a coincidence detection of data outputted from a final serial register arranged at a final end of said serial registers with a data outputted from a serial register arranged before the final serial register.
A method for testing a semiconductor memory, wherein said semiconductor memory device comprises a plurality of memory blocks, a plurality of serial registers, each of said serial registers being connected to a corresponding memory block to output serially data read from the memory block, said method comprising steps of:
- writing same data in said memory blocks at a test;
- inputting data read from said memory blocks to said serial registers;
- dividing said n serial registers into a plurality of groups, each group comprising m serial registers to connect said m serial registers in every group;
- and
- monitoring by every group of said groups a result of a coincidence detection of data outputted from a final serial register arranged at a final end of said m serial registers with data outputted from a serial register arranged immediately before the final serial register.
Dependencies are inferred from the claim text.