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US 5,521,499 AGranted
Signal controlled phase shifter
AssigneeComstream Corporation
InventorsYoav Goldenberg, Shimon Gur
Life of this patent
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AssigneeComstream Corporation
InventorsYoav Goldenberg, Shimon Gur
Estimating the term…
A clock is phase shifted by an amount controlled by the value of a control signal by establishing at least several discrete delay times to be imposed on the clock. The control signal value controls selection of the imposed discrete delay time. An analog-to-digital converter of a phase locked loop responds to intelligence representing variable phase bits and the selected phase shifted clock to control the signal value. The selected replica is derived by at least several cascaded substantially equal time delay units. In one embodiment, a multiplexer responds to the clock, and the signal value, which is Gray coded, to control connections from one of the delay units to an output terminal. In another embodiment, the number of cascaded delay units interposed between the clock and an output terminal is controlled by the signal value.
A method of discretely changing the phase of a clock as a function of time comprising deriving a signal having at least several discrete changing values as a function of time, establishing at least several discrete delay times for the clock, responding to at least several of the values of the signal to subject the clock to at least several of the established discrete delay times so there is a correspondence between the discrete delay times to which the clock is subjected and the changing values of the signal so the clock as subjected to the delays is discretely phase shifted,
A method of discretely changing the phase of a clock as a function of time comprising deriving a signal having at least several discrete changing values as a function of time, establishing at least several discrete delay times for the clock, responding to at least several of the values of the signal to subject the clock to at least several of the established discrete delay time so there is a correspondence between the discrete delay times to which the clock is subjected and the changing values of the signal so the clock as subjected to the delays is discretely phase shifted, establishing the at least several discrete delay times by applying the clock to at least several cascaded delay units having discrete delay times, the responding step being performed by changing the number of the cascaded delay units connected to the clock so that as the signal value changes, the cascaded delay units are connected to and disconnected from the clock.
Apparatus for shifting the phase of a periodic waveform in response to the value of a control signal, the phase shift being interposed between an output terminal of a source of the waveform and another output terminal, comprising at least several delay units having discrete delay times, and a controller responsive to the value of the control signal for controlling connections of the delay units between the waveform source output terminal and the another output terminal so that as the value of the control signal changes there are corresponding changes in the delay time interposed by the delay units on the periodic waveform between the waveform source output terminal and the another output terminal, the delay units being cascaded with each other, the controller responding to the value of the control signal for effectively controlling the number of the delay units cascaded between the source output terminal and the another output terminal so that as the value of the control signal changes there are corresponding changes in the number of the delay units effectively cascaded between the output terminals, the controller selecting an output of one of the delay units and coupling it to the another output terminal, the controller resetting the phase at the another output terminal in response to the phase at the another terminal shifting by approximately an integral multiple of a cycle of the periodic waveform.
Apparatus for shifting the phase of a periodic waveform in response to the value of a control signal, the phase shift being interposed between an output terminal of a source of the waveform and another output terminal, comprising at least several delay units having discrete delay times, and a controller responsive to the value of the control signal for controlling connections of the delay units between the waveform source output terminal and the another output terminal so that as the value of the control signal changes there are corresponding changes in the delay time interposed by the delay units on the periodic waveform between the waveform source output terminal and the another output terminal, the delay units being cascaded with each other, the controller responding to the value of the control signal for effectively controlling the number of the delay units cascaded between the source output terminal and the another output terminal so that as the value of the control signal changes there are corresponding changes in the number of the delay units effectively cascaded between the output terminals, the controller selecting an output of one of the delay units and coupling it to the another output terminal, the controller including a multiplexer having a first input terminal responsive to the control signal for selecting an output of one of the delay units and coupling it to the another output terminal, the multiplexer having 1,2 . . . N signal input terminals respectively responsive to 1,2 . . . N delayed replicas of the wave at output terminals of delay units 1,2 . . . N, the delay time of the delayed replica at input terminal k exceeding the delay time of the delayed replicas at input terminals 1,2 . . . (k-i), where k is respectively each of 2 . . . N, the control signal to which the multiplexer is responsive being an M bit digital reflected coded signal having a value indicating the phase shift to be introduced between the waveform source output terminal and the another output terminal, the another output terminal being an output terminal of the multiplexer, the multiplexer including (N-1) gates each having:
Apparatus for shifting the phase of a periodic waveform in response to the value of a control signal, the phase shift being interposed the phase shift being interposed between an output terminal of a source of the waveform and another output terminal, comprising at least several delay units having discrete delay times and a controller responsive to the value of the control signal for controlling connections of the delay units between the waveform source output terminal and the another output terminal so that as the value of the control signal changes there are corresponding changes in the delay time interposed by the delay units on the periodic waveform between the waveform output terminal and the another output terminal, the delay units being cascaded with each other, the controller responding to the value of the control signal for effectively controlling of the delay units cascaded between the source output terminal and the another output terminal so that as the value of the control signal changes there are corresponding changes in the numbers of the delay time units effectively cascaded between the output terminals 1, 2. . . N of said delay units being provided, delay unit 1 being connected so an output thereof is connected to said another output terminal without connections through any other of said N delay units, the controller controlling connections between input and output he terminals of the delay units and between the source output terminal and the input terminal of said delay unit 1 so that in response to the control signal having a value commanding k of said delay units to be cascaded between the source output terminal and the another output terminal the input terminal of delay unit K is connected to the source output terminal without connections through any other of said N delay elements, and the output terminal of delay unit j is connected to the input terminal of delay unit (j-1) where k is selectively any integer between 2 and N and j is selectively every integer between 2 and k.
Apparatus for shifting the phase of a periodic waveform in response to the value of a control signal, the phase shift being interposed between an output terminal of a source of the waveform and another output terminal, comprising at least several delay units having discrete delay times, and a controller responsive to the value of the control signal for controlling connections of the delay units between the waveform source output terminal and the another output terminal so that as the value of the control signal changes there are corresponding changes in the delay time interposed by the delay units on the periodic waveform between the waveform source output terminal and the another output terminal, the controll resetting the interposed delay time between the source output terminal and the another output terminal in response to the interposed delay time between the source output terminals and the another terminal shifting by approximately an integral multiple of a cycle of the periodic waveform.
Apparatus for shifting the phase of a periodic waveform in response to the value of a control signal, the phase shift being interposed between an output terminal of a source of the waveform and another output terminal, comprising at least several delay units having discrete delay times, and a controller responsive to the value of the control signal for controlling connections of the delay units between the waveform source output terminal and the another output terminal so that as the value of the control signal changes there are corresponding changes in the delay time interposed by the delay units on the periodic waveform between the waveform source output terminal and the another output terminal, the frequency of the periodic waveform and the value of the control signal and the apparatus being such that the number of delay units between the source output terminal and the another output terminal always changes monotonically as a function of time, the apparatus being included in a phase locked loop including an analog-to-digital converter responsive to an intelligence presenting set of bits, at least a portion of the intelligence having a tendency to be degraded, the converter deriving a multibit digital signal representing an amplitude of the intelligence in response to a sampling wave train derived in response to the shifted periodic waveform at the another output terminal, and means responsive to the converter for deriving signals representing frequency and phase errors between the intelligence and the shifted periodic waveform at the another output terminal, and the derived signal representing the phase error controlling the control signal.
Apparatus for shifting the phase of a periodic waveform in response to the value of a control signal, the phase shift being interposed between an output terminal of a source of the waveform and another output terminal, comprising at least several delay units having discrete delay times, and a controller responsive to the value of the control signal for controlling connections of the delay units between the waveform source output terminal and the another output terminal so that as the value of the control signal changes there are corresponding changes in the delay time interposed by the delay units on the periodic waveform between the waveform source output terminal and the another output terminal, the apparatus being included in a variable frequency oscillator, the apparatus further comprising:
Apparatus for shifting the phase of a periodic waveform in response to the value of a control signal, the phase shift being interposed between an output terminal of a source of the waveform and another output terminal, comprising at least several delay units having discrete delay times, and a controller responsive to the value of the control signal for controlling connections of the delay units between the waveform source output terminal and the another output terminal so that as the value of the control signal changes there are corresponding changes in delay time interposed by the delay units on the periodic waveform between the waveform source output terminal and the another output terminal, delay units as a whole having a reset state, the controller monotonically changing, from the reset state, the delay time interposed by the delay units on the periodic waveform as a function of time and resetting the interposed delay time to the reset state in response to the phase at the another terminal being shifted through approximately an integral multiple of a cycle of the periodic waveform.
Apparatus for shifting the phase of a periodic waveform in response to the value of a control signal, the phase shift being interposed between an output terminal of a source of the waveform and another output terminal, comprising at least several delay units having discrete delay times, and a controller responsive to the value of the control signal for controlling connections of the delay units between the waveform source output terminal and the another output terminal so that as the value of the control signal changes there are corresponding changes in delay time interposed by the delay units on the periodic waveform between the waveform source output terminal and the another output terminal, N of said delay units being provided so there is a possibility of N different discrete time delays the controller responding to the value of the control signal to selectively connect k of said N delay elements in cascaded relation with each other between the waveform source output terminal and the another output terminal while decoupling the remaining (N-k) delay units from the k cascaded units, where N is an integer and k is selectively every integer from 1 to N.
Apparatus for shifting the phase of a clock in response to a control signal representing frequency corrections to be applied to the clock comprising means responsive to the clock for delaying the clock by at least several different discrete time delays, and control means responsive to the value of the frequency correction signal for coupling the clock as delayed by the discrete time delays to an output terminal so that when the value of the frequency correction is not zero there are corresponding changes in the discrete time delays of the clock at the output terminal and when the value of the frequency correction is zero, the phase of the delayed clock at the output terminal does not change and is susceptible of having all of the discrete time delays, the frequency correction signal being very small to thereby change the phase of the delayed clock at the output terminal relative to the clock as applied to the delay circuit after many cycles of the clock have occurred.
Apparatus for shifting the phase of a clock in response to a control signal representing a phase change to be applied to the clock comprising a circuit responsive to the clock for deriving at lest several replicas of the clock, the replicas having different time delays with respect to each other, and a coupler responsive to the phase change representing signal for coupling a selected one of the replicas to an output terminal as a function of the value of the control signal, and a resetter for resetting the control signal to a predetermined value when the replica at the output terminal has shifted through an integral multiple of about one cycle of the clock.
Apparatus for shifting the phase of a clock in response to a control signal representing a phase change to be applied to the clock comprising a circuit responsive to the clock for deriving at least several replicas of the clock, the replicas having differing time delays with respect to each other, and a coupler responsive to the phase change representing signal for coupling a selected one of the replicas to an output terminal as a function of value of the control signal, the apparatus being included in a phase locked loop including an analog-to digital converter responsive to symbols to be sampled by the converter, at least a portion of the symbols having a tendency to be degraded, the converter deriving a multi-bit digital signal representing an amplitude of one of the symbols in response to a sampling wave train derived in response to the selected replica at the output terminal, and a signal deriver responsive to the converter for deriving signals representing a frequency error and phase correction of the symbols as applied to the converter relative to the selected replica, the derived phase correction signal being the control signal.
Apparatus for shifting the phase of a clock in response to a control signal representing a phase change to be applied to the clock comprising a circuit responsive to the clock for deriving at least several replicas of the clock, the replicas having differing time delays with respect to each other, and a coupler responsive to the phase change representing signal for coupling a selected one of the replicas to an output terminal as a function of the value of the control signal, the coupler when switched in response to the phase change control signal having a tendency to derive a glitch at the output terminal, and a circuit coupled to the output terminal for preventing the coupling of the glitches to the output terminal.
Apparatus for shifting the phase of a clock in response to a control signal representing a phase change to be applied to the clock comprising a circuit responsive to the clock for deriving at least several replicas of the clock, the replicas having differing time delays with respect to each other, and a counter responsive to the phase change representing signal for coupling a selected one of the replicas to an output terminal as a function of the value of the control signal, the replica deriving means including (N-1) cascaded substantially equal time delay elements designated 1, 2 . . . (N-1and the coupler for coupling including a multiplexer having N input terminals designated 0, 1, 2 . . .(N-2), input terminal 0 being responsive to the clock, input terminal k being responsive to the replica derived from delay element k, where k is selectively each of 1, 2 . . . (N-1), the multiplexer including another input responsive to the control signal and the output terminal, the phase change signal being reflected coded, the multiplexer including an array of (N-1) gates each having:
Apparatus for shifting the phase of a clock in response to a control signal representing a phase change to be applied to the clock comprising a circuit responsive to the clock for deriving at least several replicas of the clock, the replicas having differing time delays with respect to each other, and a coupler responsive to the phase change representing signal for coupling a selected one of the replicas to an output terminal as a function of the value of the control signal, the coupler including a multiplexer having a signal output terminal, N signal input terminals designated by 0, 1, 2, . . . (N-1), the multiplexer being responsive to a reflected coded signal having M bits where 2.sup.M =N, where N is an integer greater than 2, the multiplexer including:
A method of attaining phase lock between a constant frequency input and a clock having a frequency slightly different from the constant frequency comprising sampling the amplitude of the input at a sampling frequency, responding to the sampled amplitude to derive a first representation having a value equal to a frequency error between the sampling frequency and the constant frequency input, shifting the frequency of the clock by an amount determined by the value of the first representation by integrating the first representation to derive a second representation having a value commensurate with a phase shift be imposed on the clock, the phase shift to be imposed having one of at least several different discrete values, adjacent ones of said phase shift values being approximately equally spaced from each other, and imposing a delay on the clock for a time directly proportional to a selected one of the discrete values to derive the frequency shifted clock.
A method of shifting the phase of a clock to a selected one of at least several different discrete values, comprising imposing a delay on the clock for a time determined by the selected discrete value to derive the phase shifted clock so that as the selected value changes the imposed delay changes, and resetting the selected value to 0 in response to the imposed delay in the clock being shifted through an integral multiple of about one cycle of the clock.
A method of discretely changing the phase of a clock as a function of time, possibly by amounts in excess of multiples of 360.degree., comprising:
A method of changing a clock wave having a predetermined fixed frequency to derive an output wave comprising
Apparatus for changing a clock wave having a predetermined fixed frequency to derive an output wave comprising
Dependencies are inferred from the claim text.