Advanced silicon on oxide semiconductor device structure for BiCMOS integrated circuit

A fully isolated, silicon-on-oxide semiconductor integrated circuit structure, comprising in combination:

• a semiconductor wafer substrate with an oxide layer formed on a surface of said semiconductor wafer substrate;
• a thin structure bonded to said oxide layer, said thin structure comprised of a thin silicon layer and a conductive layer on a surface of said thin silicon layer adjacent said oxide layer;
• a prefabricated bipolar device region for accommodating a bipolar device including a collector and a base having an intrinsic base portion and an extrinsic base portion, said bipolar device region including a dielectric trench formed in said thin silicon layer with two opposing walls, each of said two opposing walls having a first vertical portion extending from an upper surface of said thin silicon layer to a horizontal step portion that extends toward the opposing wall thereby forming a first right angle and a first area, and a second vertical portion that extends vertically from said horizontal step portion to said conductive layer forming a second right angle and a second area, said first and second areas forming said bipolar device region, said first area of said bipolar device region being relatively wide and thin adjacent an upper surface of said thin silicon layer, said first area for accommodating a predetermined portion of said extrinsic base portion and said second area for accommodating said intrinsic base portion of said base, said extrinsic base portion being positioned on said oxide layer and having a predetermined area in contact with said collector, thereby to minimize base-to-collector junction capacitance of said bipolar device;
• and
• a MOS device region for accommodating a MOS device and including a dielectric trench formed in said thin silicon layer with two opposing walls formed in said dielectric trench, each of said two opposing walls extending vertically from said upper surface of said thin silicon layer to a horizontal dielectric wall that extends between said two opposing walls thereby isolating said MOS device region adjacent said upper surface of said thin silicon layer.