Semiconductor device and method of producing the same

A semiconductor device comprising:

• a semiconductor chip having a top surface and a bottom surface;
• a stage having a top surface and a bottom surface which makes contact with the top surface of said semiconductor chip;
• and
• a plurality of leads arranged under the bottom surface of said semiconductor chip, said leads having first ends electrically coupled to said semiconductor chip and second ends which form external terminals, each of said external terminals having a bottom surface;
• a package encapsulating said semiconductor chip and said leads so that the bottom surface of each of the external terminals is exposed at a bottom surface of said package and remaining portions of said leads are embedded within said package,
• said package having a size approximately equal to a size of said semiconductor chip in a plan view viewed from above the top surface of said semiconductor chip.

A semiconductor device comprising:

• a semiconductor chip having a top surface and a bottom surface;
• a plurality of leads arranged under the bottom surface of said semiconductor chip, said leads having first ends electrically coupled to said semiconductor chip and second ends which form external terminals, each of said external terminals having a bottom surface;
• a package encapsulating said semiconductor chip and said leads so that the bottom surface of each of the external terminals is exposed at a bottom surface of said package and remaining portions of said leads are embedded within said package;
• and
• a stage having a top surface and a bottom surface which makes contact with the top surface of said semiconductor chip, wherein the top surface of said stage forms an electrode for drawing out a potential of said semiconductor chip,
• said package having a size which is approximately the same as that of said semiconductor chip in a plan view viewed from above the top surface of said semiconductor chip.

A semiconductor device comprising:

• a semiconductor chip having a top surface and a bottom surface;
• a plurality of leads arranged under the bottom surface of said semiconductor chip, said leads having first ends electrically coupled to said semiconductor chip and second ends which form external terminals, each of said external terminals having a bottom surface;
• and
• a package encapsulating said semiconductor chip and said leads so that the bottom surface of each of the external terminals is exposed at a bottom surface of said package and remaining portions of said leads are embedded within said package,
• said package having a size which is approximately the same as that of said semiconductor chip in a plan view from above the top surface of said semiconductor chip,
• wherein the top surface of said semiconductor chip is exposed, and said bottom surface of each of the external terminals projecting beyond the bottom surface of the package.

A semiconductor device comprising:

• a semiconductor chip having a top surface and a bottom surface;
• a plurality of leads arranged under the bottom surface of said semiconductor chip, said leads having first ends electrically coupled to said semiconductor chip and second ends which form external terminals, each of said external terminals having a bottom surface;
• and
• a package encapsulating said semiconductor chip and said leads so that the bottom surface of each of the external terminals is exposed at a bottom surface of said package and remaining portions of said leads are embedded within said package,
• said package having a size which is approximately the same as that of said semiconductor chip in a plan view viewed from above the top surface of said semiconductor chip,
• wherein the top surface of said semiconductor chip is exposed and side surfaces of said semiconductor chip are exposed so that side surfaces of said package and the side surfaces of said semiconductor chip match.

A semiconductor device comprising:

• a semiconductor chip having a top surface and a bottom surface;
• a plurality of leads arranged under the bottom surface of said semiconductor chip, said leads having first ends electrically coupled to said semiconductor chip and second ends which form external terminals, each of said external terminals having a bottom surface;
• a package encapsulating said semiconductor chip and said leads so that the bottom surface of each of the external terminals is exposed at a bottom surface of said package and remaining portions of said leads are embedded within said package;
• and
• an adhesive tape for adhering the first ends of said leads to the bottom surface of said semiconductor chip,
• said package having a size which is approximately the same as that of said semiconductor chip in a plan view viewed from above the top surface of said semiconductor chip, and said bottom surface of each of the external terminals projecting beyond the bottom surface of the package.

A semiconductor device comprising:

• a semiconductor chip having a top surface and a bottom surface;
• a plurality of leads arranged under the bottom surface of said semiconductor chip, said leads having first ends electrically coupled to said semiconductor chip and second ends which form external terminals, each of said external terminals having a bottom surface;
• a package encapsulating said semiconductor chip and said leads so that the bottom surface of each of the external terminals is exposed at a bottom surface of said package and remaining portions of said leads are embedded within said package;
• radiator portions having first ends and second ends;
• and
• an adhesive tape which adheres the first ends of said radiator portions to the bottom surface of said semiconductor chip,
• said second ends being exposed at the bottom surface of said package,
• said package having a size which is approximately the same as that of said semiconductor chip in a plan view viewed from above the top surface of said semiconductor chip.

A semiconductor device comprising:

• a semiconductor chip having a top surface and a bottom surface;
• a plurality of leads arranged under the bottom surface of said semiconductor chip, said leads having first ends electrically coupled to said semiconductor chip and second ends which form external terminals, each of said external terminals having a bottom surface;
• and
• a package encapsulating said semiconductor chip and said leads so that the bottom surface of each of the external terminals is exposed at a bottom surface of said package and remaining portions of said leads are embedded within said package,
• said package having a size which is approximately the same as that of said semiconductor chip in a plan view viewed from above the top surface of said semiconductor chip,
• wherein the top surface of said semiconductor chip forms an electrode for drawing out a potential of said semiconductor chip.

A semiconductor device comprising:

• a semiconductor chip having a top surface and a bottom surface;
• a plurality of leads arranged under the bottom surface of said semiconductor chip, said leads having first ends electrically coupled to said semiconductor chip and second ends which form external terminals, each of said external terminals having a bottom surface;
• and
• a package encapsulating said semiconductor chip and said leads so that the bottom surface of each of the external terminals is exposed at a bottom surface of said package and remaining portions of said leads are embedded within said package,
• said package having a size which is approximately the same as that of said semiconductor chip in a plan view viewed from above the top surface of said semiconductor chip,
• wherein said leads have a thickness t, and the external terminals of said leads project from the bottom surface of said package by a distance h, where 0<h<t.

A semiconductor device comprising:

• a semiconductor chip having a top surface and a bottom surface;
• a plurality of leads arranged under the bottom surface of said semiconductor chip, said leads having first ends electrically coupled to said semiconductor chip and second ends which form external terminals, each of said external terminals having a bottom surface;
• and
• a package encapsulating said semiconductor chip and said leads so that the bottom surface of each of the external terminals is exposed at a bottom surface of said package and remaining portions of said leads are embedded within said package,
• said package having a size which is approximately the same as that of said semiconductor chip in a plan view viewed from above the top surface of said semiconductor chip,
• wherein each of the external terminals have an end portion which slightly projects from a side surface of said package.

A semiconductor device comprising:

• a semiconductor chip having a top surface and a bottom surface;
• a plurality of leads arranged under the bottom surface of said semiconductor chip, said leads having first ends electrically coupled to said semiconductor chip and second ends which form external terminals, each of said external terminals having a bottom surface;
• and
• a package encapsulating said semiconductor chip and said leads so that the bottom surface of each of the external terminals is exposed at a bottom surface of said package and remaining portions of said leads are embedded within said package,
• said package having a size which is approximately the same as that of said semiconductor chip in a plan view viewed from above the top surface of said semiconductor chip,
• wherein each of the external terminals have an end portion which matches a side surface of said package.

A semiconductor device comprising:

• a semiconductor chip having a top surface and a bottom surface;
• a plurality of leads arranged under the bottom surface of said semiconductor chip, said leads having first ends electrically coupled to said semiconductor chip and second ends which form external terminals, each of said external terminals having a bottom surface;
• and
• a package encapsulating said semiconductor chip and said leads so that the bottom surface of each of the external terminals is exposed at a bottom surface of said package and remaining portions of said leads are embedded within said package,
• said package having a size which is approximately the same as that of said semiconductor chip in a plan view viewed from above the top surface of said semiconductor chip,
• wherein each of the external terminals have an end portion which is slightly receded from a side surface of said package, and said bottom surface of each of the external terminals projecting beyond the bottom surface of the package.

A semiconductor device comprising:

• a semiconductor chip having a top surface and a bottom surface;
• a plurality of leads arranged under the bottom surface of said semiconductor chip, said leads having first ends electrically coupled to said semiconductor chip and second ends which form external terminals, each of said external terminals having a bottom surface;
• and
• a package encapsulating said semiconductor chip and said leads so that the bottom surface of each of the external terminals is exposed at a bottom surface of said package and remaining portions of said leads are embedded within said package, wherein dimples or grooves are formed on at least the bottom surface of the external terminals, so as to increase the surface area,
• said package having a size which is approximately the same as that of said semiconductor chip in a plan view viewed from above the top surface of said semiconductor chip, and said bottom surface of each of the external terminals projecting beyond the bottom surface of the package.