PLL circuit having a multiloop, and FM receiving method and apparatus able to utilize the same

A PLL circuit comprising:

• a VCO for generating an output signal having a frequency which is variable in accordance with a control voltage;
• first frequency-dividing means for frequency-dividing the output signal sent from said VCO to produce a first digital feedback signal;
• second frequency-dividing means for frequency-dividing the first digital feedback signal to produce a second digital feedback signal;
• reference signal generating means for generating both an analog reference signal and a digital reference signal each having a reference frequency;
• frequency-multiplying means for frequency-multiplying the analog reference signal to produce the frequency-multiplied analog reference signal;
• first phase error detecting means for comparing a phase of the second digital feedback signal with a phase of the digital reference signal to obtain a first phase error signal representing a phase error there-between and integrating the first phase error signal;
• second phase error detecting means for comparing the phase of the second digital feedback signal with a phase of the analog reference signal to obtain a second phase error signal representing a phase error therebetween, and for adding the second phase error signal to the integrated first phase error signal and extracting the low frequency components from the added signal to obtain a composite phase error signal;
• and
• third phase error detecting means for comparing a phase of the first digital feedback signal with a phase of the frequency-multiplied analog reference signal to obtain a third phase error signal representing a phase error therebetween, and for adding the third phase error signal to the composite phase error signal and extracting the low frequency components from the added signal to produce the control voltage for said VCO.

A multi-channel FM receiving apparatus for receiving a multi-channel FM input signal having respective channels with center frequencies located at intervals of a predetermined frequency and within a first frequency band, said apparatus comprising:

• first local oscillation signal producing means for producing a first local oscillation signal which has a variable frequency at a plurality of integral multiples of the predetermined frequency and within a second frequency band which does not overlap with said first frequency band;
• first intermediate frequency signal producing means for receiving the first local oscillation signal to up-convert the FM input signal, thereby producing a first intermediate frequency signal having a frequency which is different from the frequencies corresponding to two times the center frequencies of the channels of the FM input signal and which does not overlap with said first and second frequency bands;
• second local oscillation signal producing means for producing a second local oscillation signal having a fixed frequency which does not overlap with said first and second frequency bands and a frequency band of the first intermediate frequency signal;
• and
• second intermediate frequency signal producing means for receiving the second local oscillation signal to down-convert the first intermediate frequency signal, thereby producing a second intermediate frequency signal;
• and,
• wherein said first local oscillation signal producing means includes a PLL circuit comprising:
• a VCO for generating an output signal having a frequency which is variable in accordance with a control voltage;
• first frequency-dividing means for frequency-dividing the output signal sent from said VCO to produce a first digital feedback signal;
• second frequency-dividing means for frequency-dividing the first digital feedback signal to produce a second digital feedback signal;
• reference signal generating means for generating both an analog reference signal and a digital reference signal each having a reference frequency;
• frequency-multiplying means for frequency-multiplying the analog reference signal to produce the frequency-multiplied analog reference signal;
• first phase error detecting means for comparing a phase of the second digital feedback signal with a phase of the digital reference signal to obtain a first phase error signal representing a phase error therebetween and integrating the first phase error signal;
• second phase error detecting means for comparing the phase of the second digital feedback signal with a phase of the analog reference signal to obtain a second phase error signal representing a phase error therebetween, and for adding the second phase error signal to the integrated first phase error signal and extracting the low frequency components from the added signal to obtain a composite phase error signal;
• and
• third phase error detecting means for comparing a phase of the first digital feedback signal with a phase of the frequency-multiplied analog reference signal to obtain a third phase error signal representing a phase error therebetween, and for adding the third phase error signal to the composite phase error signal and extracting the low frequency components from the added signal to produce the control voltage for said VCO.