Satellite radio receiver

A satellite radio receiver of a satellite receiving facility which includes signal feeds from a receiving antenna and at least one frequency converter, the satellite radio receiver comprising:

• a PLL local oscillator which is tunable in one of a large step range and in a small step range in response to a control signal,
• a PSK demodulator circuit with a carrier oscillator and having an output signal,
• a sync signal evaluation circuit responsive to the output signal of the demodulator circuit for providing a recovery output signal,
• the output signal of the sync signal evaluation circuit and a version of the output signal of the PSK demodulator circuit after being operated upon by a loop filter and a comparator being coupled to inputs of a control circuit which provides the control signal for tuning the PLL local oscillator in the large step range outside a lock-in range of the demodulator circuit when one of the version of the output signal of the demodulator circuit and the output signal of the sync signal evaluation circuit are not recognized by the control circuit so that no signal is received by the PLL oscillator from the control circuit, and sharply tuned in a small step range within the lock-in range when one of the version of the output signal of the demodulator circuit and the output signal of the sync signal evaluation circuit are recognized and signals are received by the PLL oscillator from the control circuit,
• a comparator circuit which compares the version of the output signal of the demodulator circuit with an upper and a lower threshold value,
• a pair of output terminals of the comparator circuit being connected with the control circuit whereby signal at one output terminal determines a first direction of tuning and signal at another output terminal determines the other direction of tuning, the version of the output signal of the demodulator circuit being the signals at the output terminals of the comparator circuit, and
• the sync signal evaluation circuit includes a circuit for evaluation of an error rate of received signals from the demodulator circuit and provides an error signal, an integration means for integrating the error signals in a pre-determined manner with pre-determined time constants, and transition means responsive to an output signal of the integration means and having a threshold referenced to a reference voltage for determining the recovery output signal coupled to the control circuit for determining the switching-over of the large and small step ranges.