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US 5,517,669 AGranted
Cyclic data communication system
AssigneeHitachi, Ltd.
InventorsYoshinori Ohkura, Takuji Hamada, Shunji Inada, Shinichiro Yamaguchi, Hiroshi Tomizawa
Life of this patent
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Abstract
A data communication system carries out transmission and reception of periodic data between a plurality of computers, and especially an improved data communication system which aims at more effective utilization of a system bus in each computer and which also aims at more effective utilization of a data transmission channel transmitting periodic data, so that the load imposed on the system bus during transfer of periodic data in each computer can be minimized, and the rate of occupation of the data transmission channel during transmission and reception of periodic data can also be minimized.
Claims19
A data communication system comprising:
- A) a data transmission channel;
- and
- B) a plurality of control computers coupled to said data transmission channel in common and each of said control computers including:
- 1) at least one CPU,
- 2) a main memory,
- 3) a communication controller having:
- a) a built-in control portion for controlling data transmission and reception of cyclic data to and from said data transmission channel, and
- b) a built-in memory for storing cyclic data, and
- 4) a system bus used for data transfer among said CPU, said main memory, and said communication controller, wherein:
- C) each communication controller:
- 1) receives cyclic data, accessible at least within its own control computer from said data transmission channel,
- 2) stores all cyclic data received in the main memory of said control computer;
- 3) selects, out of the cyclic data stored in the main memory associated with its own control computer which can possibly be rewritten by data processing executed in said own control computer, that cyclic data actually rewritten by said own control computer, and
- 4) reads and transmits said selected cyclic data to other control computers through said data transmission channel;
- and
- D) the CPU of each control computer accesses the cyclic data from its own main memory only.
13 more elements
A data communication system comprising:
- A) data transmission channel;
- and
- B) a plurality of control computers coupled to said data transmission channel in common and each of said control computers including:
- 1) at least one CPU,
- 2) a main memory,
- 3) a communication controller having:
- a) a built-in control portion for controlling data transmission and reception to and from said data transmission channel, and
- b) a built-in memory for storing cyclic data, and
- 4) a system bus used for data transfer among said CPU, said main memory, and said communication controller, wherein:
- C) each communication controller:
- 1) receives cyclic data, accessible at least within said control computer of which it is part from said data transmission channel,
- 2) stores all cyclic data received in the main memory of said control computer;
- 3) reads all cyclic data which can be possibly rewritten within its own control computer when reading the cyclic data stored in the main memory from its own control computer to transmit to other control computers,
- 4) compares all of said cyclic data with previously read cyclic data stored in its own built-in memory for storing cyclic data, and
- 5) transmits to other control computers through said data transmission channel only that cyclic data, the value of which has changed;
- and
- D) the CPU of each control computer accesses the cyclic data from its own main memory only.
14 more elements
A data communication system comprising:
- A) data transmission channel;
- and
- B) a plurality of control computers coupled to said data transmission channel in common and each of said control computers including:
- 1) at least one CPU,
- 2) a main memory,
- 3) a communication controller having:
- a) a built-in control portion for controlling data transmission and reception to and from said data transmission channel, and
- b) a built-in memory for storing cyclic data, and
- 4) a system bus used for data transfer among said CPU, said main memory, and said communication controller, wherein:
- C) each communication controller:
- 1) receives cyclic data, accessible at least within its own control computer from said data transmission channel, and
- 2) stores all cyclic data received in the main memory of its own control computer;
- and
- 3) transmits the cyclic data transferred from its own CPU to other control computers through said data transmission channel;
- and
- D) each CPU:
- 1) accesses the cyclic data from its own main memory only, and
- 2) in the case where a rewrite request generates for the cyclic data stored in its own main memory, transfers rewritten data to said main memory and to said communication controller.
15 more elements
Dependencies are inferred from the claim text.