Program controlled processor wherein vector distributor and vector coupler operate independently of sequencer

A program controlled processor comprising:

• a plurality of vector processors, said plurality of vector processors executing a plurality of parallel instructions including parallel vector instructions, and executing vector operations based on the parallel vector instructions in pipeline processing;
• a scalar processor, said scalar processor connected via a bus to said plurality of vector processors and executing a scalar operation;
• an instruction memory for storing program instructions;
• a sequencer for controlling the instruction memory;
• a decoder for interpreting program instructions received from the sequencer, for controlling all of said vector processors so that said processors execute an identical operation if an instruction to be executed is a parallel vector instruction and for controlling the scalar processor to execute a scalar operation if an instruction to be executed is not a parallel vector instruction;
• a vector distributor receiving two series of input vector data and for dividing each series of input vector data into a plurality of block vectors, wherein a number of block vectors is the same as that of vector processors, and for sending the block vectors to corresponding vector processors;
• and
• a vector coupler for coupling block vectors obtained by the vector operations in said plurality of vector processors to send an output vector;
• wherein each of said vector processors comprises:
• two input memories for storing two series of input block vectors;
• a vector processor for executing a vector operation on data including the block vectors received from the input;
• a first output memory for storing a vector result of the vector operation, the first output memory being connected to said vector coupler and to the vector processor, and a second output memory for storing a scalar result of the vector operation, the second output memory being connected to the bus between the scalar processor and the plurality of vector processors;
• and wherein each of said input memories and said first output memory for storing block vectors comprises a plurality of buffer memories, each for storing block vectors;
• if block vector data is written in one of the plurality of buffer memories of each of said input memories by said vector distributor, then block vector data can be read from another of the plurality of buffer memories by said vector processor, and if block vector data is written in one of the plurality of buffer memories of each of said first output memories by said vector processor, then block vector data can be read from another of the plurality of buffer memories by said vector coupler, so that said distributor, said vector coupler and said vector processor operate independently of each other;
• and
• wherein if an instruction to be executed is a parallel vector instruction, of which a result is a vector, the vector processor stores the results of the processing in the vector processor and outputs the results to the vector coupler while if an instruction to be executed is a parallel vector instruction, of which a result is a scalar, the scalar processor receives the scalar results from the plurality of vector processors via the bus between said scalar processor and said plurality of vector processors;
• and
• wherein the program controlled processor further comprises an address generator for controlling access to the input memory or the first output memory to write or read 2.sup.nx .times.2.sup.ny) of (2.sup.nx .times.2.sup.ny .times.2.sup.mx .times.2.sup.my) data to or from (2.sup.mx .times.2.sup.my) input memory elements or the first output memory in the program controlled processor where nx, ny, mx and my are natural numbers and wherein nx, ny, mx and my correspond to a rectangular image area of (2.sup.nx+mx).times.(2.sup.ny+my) pixels which is divided into a plurality of image signals of rectangular blocks each comprising 2.sup.nx .times.2.sup.ny pixels;
• and
• wherein nx=ny=n and mx=my=m, and said address generator comprises:
• an (n+n+m+m)-bit address counter for counting data accesses when data access begins;
• a switch circuit comprising i address selectors (1.ltoreq.i.ltoreq.n) for selecting bit (n+i) or bit (n+m+i) and j memory address selectors (1.ltoreq.j.ltoreq.m) for selecting bit (n+n+j) when bit (n+i) is selected by the i address selectors and for selecting bit (n+j) when bit (n+m+i) is selected by the i address selectors;
• and
• an access controller for sending memory access signals to (2.sup.m .times.2.sup.m) memory elements, wherein i, j, m and n are natural numbers;
• wherein bits 1 to n of outputs of the address counter and the i address selectors are output as an address to 2.sup.2.times.m memory elements, and outputs of the j memory address selectors and bits (n+n+m+1) to (n+n+m+m) of the address counter are sent to the access controller.

A program controlled processor comprising:

• a plurality of vector processors, said plurality of vector processors executing a plurality of parallel instructions including parallel vector instructions, and executing vector operations based on the parallel vector instructions in pipeline processing;
• a scalar processor, said scalar processor connected via a bus to said plurality of vector processors and executing a scalar operation;
• an instruction memory for storing program instructions;
• a sequencer for controlling the instruction memory;
• a decoder for interpreting program instructions received from the sequencer, for controlling all of said vector processors so that said processors execute an identical operation if an instruction to be executed is a parallel vector instruction and for controlling the scalar processor to execute a scalar operation if an instruction to be executed is not a parallel vector instruction;
• a vector distributor receiving two series of input vector data and for dividing each series of input vector data into a plurality of block vectors, wherein a number of block vectors is the same as that of vector processors, and for sending the block vectors to corresponding vector processors;
• and
• a vector coupler for coupling block vectors obtained by the vector operations in said plurality of vector processors to send an output vector;
• wherein each of said vector processors comprises:
• two input memories for storing two series of input block vectors;
• a vector processor for executing a vector operation on data including the block vectors received from the input memories;
• a first output memory for storing a vector result of the vector operation, the first output memory being connected to said vector coupler and to the vector processor, and a second output memory for storing a scalar result of the vector operation, the second output memory being connected to the bus between the scalar processor and the plurality of vector processors;
• and wherein each of said input memories and said first output memory for storing block vectors comprises a plurality of buffer memories, each for storing block vectors;
• if block vector data is written in one of the plurality of buffer memories of each of said input memories by said vector distributor, then block vector data can be read from another of the plurality of buffer memories by said vector processor, and if block vector data is written in one of the plurality of buffer memories of each of said first output memories by said vector processor, then block vector data can be read from another of the plurality of buffer memories by said vector coupler, so that said distributor, said vector coupler and said vector processor operate independently of each other;
• and
• wherein if an instruction to be executed is a parallel vector instruction, of which a result is a vector, the vector processor stores the results of the processing in the vector processor and outputs the results to the vector coupler while if an instruction to be executed is a parallel vector instruction, of which a result is a scalar, the scalar processor receives the scalar results from the plurality of vector processors via the bus between said scalar processor and said plurality of vector processors;
• and
• wherein the program controlled processor further comprises an address generator for controlling access to the input memory or the first output memory to write or read (2.sup.nx .times.2.sup.ny) of (2.sup.nx .times.2.sup.ny .times.2.sup.mx .times.2.sup.my) data to or from (2.sup.mx .times.2.sup.my) input memory elements or the first output memory in the program controlled processor where nx, ny, mx and my are natural numbers and wherein nx, ny, mx and my correspond to a rectangular image area of (2.sup.nx+mx).times.(2.sup.ny+my) pixels which is divided into a plurality of image signals of rectangular blocks each comprising 2.sup.nx .times.2.sup.ny pixels;
• and
• wherein mx=my=m and nx=ny=n, and said address generator comprises:
• an (n+n+m+m+1)-bit address counter for counting data accesses when data access begins;
• i address selectors (1.ltoreq.i.ltoreq.n) for selecting bit (n+i) or bit (n+m+i);
• j memory address selectors (1.ltoreq.j.ltoreq.m) for selecting bit (n+n+j) when bit (n+i) is selected by the i address selectors, and for selecting bit (n+j) when bit (n+m+i) is selected by the i address selectors;
• a terminate signal selector for selecting bit (2.times.n+2.times.m+1) or bit (2.times.n+2.times.m) according to a memory number selection signal for selecting access to 2.sup.2.times.m memory elements or 2.sup.m memory elements;
• and
• an access controller for sending memory access signals to (2.sup.m .times.2.sup.m) memory elements, wherein i, j, m and n are natural numbers;
• wherein bits 1 to n of the address counter and i address selector outputs are output as an address to the 2.sup.2.times.m memory elements, and outputs of the j memory address selector and bits (n+n+m+1) to (n+n+m+m) of the address counter are input to the access controller, and the terminate signal selector selects bit (n+n+m+m+1) if the memory number selection signal selects the access to the 2.sup.2.times.m memory elements, and selects bit (n+n+m+m) if the memory number selection signal selects the access to the 2.sup.m memory elements.