Method for testing design timing parameters using a timing shell generator
AssigneeLSI Logic Corporation
InventorsDavid Gluss, Georgia Lazana, Douglas Boyle
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AssigneeLSI Logic Corporation
InventorsDavid Gluss, Georgia Lazana, Douglas Boyle
Estimating the term…
A method for testing the timing parameters of a system design is presented, especially suited for use in testing for timing violations between the pins of a semiconductor device. A description of the timing constraints of the various modules of a design is written in a common non-technical vernacular, and functions as an input file. A Timing Shell Generator converts the input file description into a simulator-environment-compatible output code-language file description. The output code-language file is operative to implement the timing constraints of the original input file during simulation such that any violations of the prescribed timing constraints are indicated to the tester who can then take appropriate action.
A method for providing user-specified timing constraints to a simulator of system operation, between functional modules of a design for a system including a plurality of modules, each module having one or more terminals and its own individual operational parameters, the user-specified timing constraints being converted from a timing vernacular language to timing constraints in a behavioral simulation language that is compatible with the simulator, the method comprising the steps of:
Dependencies are inferred from the claim text.