Segment register file read and write pipeline

Within an address generation unit of a processor, an apparatus for accessing a segment register file, said apparatus comprising:

• a clock signal for referencing pipestages of an instruction pipeline;
• read logic for reading information from a segment register file during a first clock phase of a first pipestage of a first instruction;
• protection logic for checking if said first instruction may update said segment register file, said protection logic operable during a second pipestage of said first instruction;
• write logic for writing information into said segment register file, said information associated with said first instruction, said write logic operable during a second clock phase of a third pipestage of said first instruction;
• and
• wherein said read logic is also for reading information from said segment register file during a first clock phase of a first pipestage of a second instruction, wherein said first pipestage of said second instruction and said third pipestage of said first instruction occur concurrently.

Within an address generation unit of a processor, an apparatus for accessing segment information, said apparatus comprising:

• a buffer means for containing segment information, said segment information for maintaining memory segments of said processor;
• a clock signal for referencing pipestages of instruction pipelines;
• read means for reading information associated with a first instruction from said buffer means during a first clock phase of said clock signal;
• and
• write means for writing information associated with said first instruction into said buffer means, said write means operable during a second clock phase of said clock signal, wherein said first clock phase and said second clock phase are alternates.

A pipelined processor for executing instructions and processing information, said processor comprising:

• a clock signal for referencing pipestages of an instruction pipeline;
• an issue unit communicatively coupled to receive instruction information and for issuing instructions;
• an execution unit for executing issued instructions and writing back result information to a register file;
• and
• an address generation unit for computing memory addresses associated with memory access operations and for processing segment register operations, said address generation unit comprising:
• a segment register file for containing segment information, said segment information for maintaining memory segments of said processor;
• read logic for reading information associated with a first instruction from said segment register file during a first clock phase of said clock signal;
• and
• write logic for writing information associated with said first instruction into said segment register file, said write logic operable during a second clock phase of said clock signal, wherein said first clock phase and said second clock phase are alternates.

A computer system comprising:

• a system bus for providing a communication pathway;
• a memory array coupled to said system bus for providing addressable space for instructions and data, said memory array capable of segmentation;
• a user interface coupled to said bus for receiving information and transmitting information;
• and
• a pipelined processor coupled to said bus for executing instructions and processing data, said processor comprising an address generation unit for computing memory addresses associated with memory access operations and for processing segment register operations, said address generation unit comprising:
• a clock signal for referencing pipestages of an instruction pipeline;
• a segment register file for containing segment information, said segment information for maintaining memory segments of said memory array;
• read logic for reading information associated with a first instruction from said segment register file during a first clock phase of said clock signal;
• and
• write logic for writing information associated with said first instruction into said segment register file, said write logic operable during a second clock phase of said clock signal, wherein said first clock phase and said second clock phase are alternates.

In an address generation unit of a processor, a method of accessing segment information, said method comprising the steps of:

• providing a clock signal for referencing pipestages of an instruction pipeline;
• providing a segment register file for containing memory segment information;
• reading said segment register file during a first clock phase of said clock signal;
• writing said segment register file during a second clock phase of said clock signal, wherein said first clock phase and said second clock phase are alternates.

In an address generation unit, a method of accessing a segment register file to avoid resource conflicts, said method comprising the steps of:

• (a) providing a clock signal for referencing pipestages of an instruction pipeline;
• (b) reading said segment register file during a first clock phase of a first pipestage of a first instruction;
• (c) performing a protection check during a second pipestage of said first instruction;
• (d) writing said segment register file during a second clock phase of a third pipestage of said first instruction;
• and
• (e) reading said segment register file during a first clock phase of a first pipestage of a second instruction, wherein said first clock phase and said second clock phase are alternates and wherein said steps of (d) and (e) occur concurrently.