US 5,517,651 A · Method and apparatus for loading a segment register in a microprocessor capable of operating in multiple modes

Abstract

A microprocessor contains an address generation unit, including a segment block, for loading descriptor data and a segment selector in a segment register. Two descriptor loads from a global descriptor table (GDT) and a local descriptor table (LDT) are executed. A 64 bit global descriptor from the GDT is loaded into a temporary register, and a 64 bit local descriptor from the LDT is also loaded into a separate temporary register. If a table indicator bit in the segment selector indicates use of the GDT, then the descriptor data from the GDT is selected. Alternatively, if the table indicator bit in the segment selector indicates the use of the LDT, then the descriptor data from the LDT is selected. The segment block splits the 64 bit descriptor data selected into two 32 bit quantities. The two 32 bit data quantities are input to a test programmable logic array (PLA). The test PLA checks for permission violations, or faults, and detects the need for special handling of the register segment load operation. If a fault violation occurs, the segment block signals a fault exception. If no fault is detected, then the segment block loads the two 32 bit descriptor data segments, along with the selector, into the appropriate segment register. If special handling is required, a conditional indirect branch is utilized to reach the handler.

Claims39

Dependent claims

A method for loading a segment register in a microprocessor operable in multiple modes, said method comprising the steps of:

receiving a segment selector for a corresponding segment register load, said segment selector specifying a descriptor stored in a corresponding descriptor table;
issuing a plurality of conditional load operations to a memory subsystem, wherein each of said plurality of conditional load operations specifies loading of a descriptor from a corresponding descriptor table;
checking, in said memory subsystem, said segment selector associated with each of said plurality of conditional load operations to determine whether said segment selector specifies a descriptor table corresponding to said descriptor;
executing, in said memory subsystem, one of said plurality of conditional load operations if said segment selector specifies a descriptor table corresponding to said descriptor;
writing said descriptor corresponding to said segment selector to a temporary segment register if said segment selector specifies said descriptor table corresponding to said descriptor;
writing invalid data to said temporary segment register and identifying said invalid data as invalid if said segment selector does not specify a descriptor table corresponding to said descriptor:
and
loading said segment register, by utilizing said descriptor and selector, in accordance with an operating mode of said microprocessor.

5 more elements

An apparatus for loading a segment register in a microprocessor, wherein said microprocessor is operable in multiple modes, said apparatus comprising:

memory, coupled to said microprocessor, for storing a plurality of descriptors arranged in a plurality of descriptor tables;
a memory subsystem, coupled to said memory, for interfacing said microprocessor to memory;
a segment block, including a microcode execution unit, and a plurality of temporary registers, coupled to said memory subsystem, said segment block being constructed to receive a segment selector for a corresponding segment register load, said segment selector specifying a descriptor stored in a corresponding descriptor table, said microcode execution unit being constructed to issue a plurality of conditional load operations to said memory subsystem, wherein each of said plurality of conditional load operations specifies loading of a descriptor from a corresponding descriptor table, said memory subsystem for executing one of said plurality of conditional load operations when said segment selector specifies a descriptor table corresponding to said descriptor, said memory subsystem for checking said segment selector and for writing said descriptor to said temporary register if said segment selector specifies a descriptor table corresponding to said descriptor, said memory subsystem for writing invalid data to said temporary register and for identifying said invalid data as invalid if said segment selector does not specify a descriptor corresponding to said descriptor table, and said microcode execution unit comprising a load operation to load said segment register, by utilizing said descriptor and selector, in accordance with an operating mode of said microprocessor.

A microprocessor comprising:

an instruction fetch circuit for fetching instructions;
an instruction decoder, coupled to said instruction fetch circuit, for decoding and issuing said instructions fetched;
memory, coupled to said microprocessor, for storing a plurality of descriptors arranged in a plurality of descriptor tables;
a memory subsystem coupled to said memory for interfacing said microprocessor to said memory;
an address generation unit, coupled to an out-of-order cluster and said memory subsystem, for generating addresses for said memory, said address generation unit comprising a segment block, including a microcode execution unit, and a plurality of temporary registers, coupled to said memory subsystem, said segment block being constructed to receive a segment selector for a corresponding segment register load from said out-of-order cluster, said segment selector specifying a descriptor stored in a corresponding descriptor table, said microcode execution unit being constructed to issue a plurality of conditional load operations to said memory subsystem, wherein each of said plurality of conditional load operations specifies loading of a descriptor from a corresponding descriptor table, said memory subsystem for executing one of said plurality of conditional load operations when said segment selector specifies a descriptor table corresponding to said descriptor, said memory subsystem for checking said segment selector and for writing said descriptor to said temporary register if said segment selector specifies a descriptor table corresponding to said descriptor, said memory subsystem for writing invalid data to said temporary register and for identifying said invalid data as invalid if said segment selector does not specify a descriptor corresponding to said descriptor table, said temporary register being constructed to receive a descriptor from each conditional load operation not canceled, and said microcode execution unit comprising a load operation to load said segment register, by utilizing said descriptor and selector, in accordance with an operating mode of said microprocessor;
and
retirement logic for reordering said instructions in said original program order.

4 more elements

Dependencies are inferred from the claim text.

Method and apparatus for loading a segment register in a microprocessor capable of operating in multiple modes

Life of this patent

Method and apparatus for loading a segment register in a microprocessor capable of operating in multiple modes

Life of this patent

Abstract

Claims39