Bridge for a power managed computer system with multiple buses and system arbitration

A bridge for interfacing between buses of a a computer system that has a first bus, a second bus, first bus devices that are first bus-compliant, second bus devices that are non-first bus-compliant, a central processing unit (CPU) and a power management device that places the computer system into a suspend mode, a resume mode and an active mode, the bridge comprising:

• an arbitration device for arbitrating among the first bus-compliant devices and the non-first bus-compliant devices for control of the computer system, and responsive to the power management device to controllably suspend arbitration when the power management device indicates that the suspend mode is being entered;
• wherein the arbitration device is a multi-tiered arbiter that includes a first bank arbiter through which the first bus-compliant devices arbitrate, a second bank arbiter through which the non-first bus-compliant devices arbitrate, and a central bank arbiter which arbitrates among the first and second bank arbiters to provide arbitration for the system among the first bus-compliant devices and the non-first bus-compliant devices.