Method for testing a test architecture within a circuit

A method for testing an integrated circuit, the method comprising the steps of:

• a) receiving integrated circuit topology information of the integrated circuit, wherein the integrated circuit has a test architecture which allows the integrated circuit to participate in system-level testing operations, the integrated circuit topology information including test architecture topology information, the integrated circuit topology information being stored as a circuit netlist via computer-readable media;
• b) obtaining a boundary scan description of the test architecture of the integrated circuit wherein the boundary scan description defines various physical features of the test architecture and is stored via computer readable media;
• c) generating, based on the boundary scan description, test parameters for use by a logic simulation, wherein the logic simulation is used to test the integrated circuit;
• d) exercising the integrated circuit via the logic simulation and the monitoring the excerising of the integrated circuit for any occurrence of an error the error being detected based on at least a portion of the test parameters;
• and
• e) obtaining an error correction for the error in response to the error being detected.

A method for producing an integrated circuit, the method comprising the steps of:

• receiving integrated circuit topology information for the integrated circuit from an integrated circuit netlist stored in computer readable memory, wherein the integrated circuit has a boundary scan test architecture, and the integrated circuit topology information includes test architecture topology information;
• generating a boundary scan description of the test architecture based on the test architecture topology information;
• selecting a selected test from a predetermined set of test methodologies for testing the test architecture;
• generating test parameters for a logic simulation based on the boundary scan description and the selected test;
• testing the test architecture via simulation by utilizing a logic simulation which exercises the integrated circuit netlist based on the test parameters and the integrated circuit topology information;
• and
• fabricating the integrated circuit including the test architecture when the step of testing indicates that no errors occurred within the test architecture.

A method for testing a test architecture within an integrated circuit, the method comprising:

• receiving integrated circuit topology information for an integrated circuit from computer memory;
• receiving a boundary scan description of a test architecture, wherein the boundary scan description is based on the integrated circuit topology information from the computer memory;
• obtaining test architecture topology information, wherein the test architecture topology information is based on the boundary scan description and the integrated circuit topology information;
• combining the integrated circuit topology information and the test architecture topology information to produce combined circuit topology information;
• selecting a test from a predetermined set of test methodologies for testing the test architecture within the combined circuit topology information;
• generating test parameters for a logic simulation based on the boundary scan description and the selected test;
• and
• testing the test architecture with the logic simulation based on the test parameters and the combined circuit topology information.

A method for testing JTAG circuitry within an integrated circuit, the method comprising the steps of:

• providing the JTAG circuitry in a circuit netlist data file;
• reading the circuit netlist data file obtain JTAG topology information relating to the JTAG circuitry;
• generating a boundary scan description of the JTAG circuitry based upon the JTAG topology information;
• selecting a selected JTAG circuitry test from a plurality of potential JTAG circuitry tests displayed via a graphical user interface on a computer screen;
• generating test vectors for use by a simulation tool wherein the test vectors are based upon the selected JTAG circuitry test and the boundary scan description;
• and
• testing the JTAG test architecture using the test vectors to ensure that the JTAG circuitry is compliant with JTAG standards.

A tester for testing a test circuit portion of an integrated circuit wherein the integrated circuit and test circuit portion are represented in a netlist data file, the tester comprising:

• means for receiving the netlist data file and extracting test circuit topology information from the netlist data file;
• means for generating a boundary scan description of the test circuit portion based upon the test circuit topology information;
• means for selecting a selected test from a plurality of predetermined tests wherein the tests are used by a simulation program which exercises the netlist data file to determine correct operation of the test circuit portion;
• means for generating test parameters for use by the simulation program to determine correct operation of the test circuit portion, the test parameters being based upon the boundary scan description and the selected test;
• and
• means for testing the test circuit portion with the simulation program by using the test parameters and the netlist data file.

A tester, stored on computer readable storage, for testing a test circuit portion of an integrated circuit wherein the integrated circuit and test circuit portion are represented in a netlist data file, the computer readable storage comprising:

• a plurality of computer instructions for receiving the netlist data file and extracting test circuit topology information from the netlist data file;
• a plurality of computer instructions for generating a boundary scan description of the test circuit portion based upon the test circuit topology information;
• a plurality of computer instructions for selecting a selected test from a plurality of predetermined tests wherein the tests are used by a simulation program which exercises the netlist data file to determine correct operation of the test circuit portion;
• a plurality of computer instructions for generating test parameters for use by the simulation program to determine correct operation of the test circuit portion, the test parameters being based upon the boundary scan description and the selected test;
• and
• a plurality of computer instructions for testing the test circuit portion with the simulation program by using the test parameters and the netlist data file.