System for controlling an internally-installed cache memory

A cache memory control system internally installed in a CPU, comprising:

• a first memory to be accessed by an address having A bits concatenated with B bits;
• a second memory to be accessed by an address having A bits, and said second memory comprising 2.sup.B regions in an address designated by A bits;
• means for writing information into said address of said first memory designated by said A bits concatenated with B bits and for writing said information into one of 2.sup.B regions corresponding to a binary code of B bits in said address designated by said A bits in said second memory during a registration operation;
• comparison means for, when external information including said A bits and said information is provided, and said second memory is accessed by using A bits of said external information, reading the content of said address designated by A bits and comparing the content of respective 2.sup.B regions which are read-out with said information of said external information, and detecting a region in which the read-out information accords with said information of said external information;
• converting means for converting through an encoding operation a position information of one of the regions 2.sup.B at which the read-out information accords with said information of said external information;
• and
• invalidating means for combining said B bits with said A bits to provide A bits concatenated with B bits, thereby accessing said first memory and invalidating the content of the accessed address of said first memory by using said A bits concatenated with B bits.

A cache memory control system, comprising:

• a memory to be accessed by a physical address on an external address bus, said physical address being composed of A bits concatenated with B bits, said A bits comprising an offset portion of said physical address on the external address bus;
• an address monitor portion to be accessed by said A bits;
• comparing means for reading a physical address from said address monitor portion by using said A bits of said offset portion of said physical address on said external address bus, for comparing the physical address read from the address monitor portion with the physical address carried on the external address bus, to select a position information corresponding to one of 2.sup.B regions;
• conversion means for encoding the position information obtained as a result of the comparisons to produce converted information comprising B bits;
• and
• invalidation control means for forming said A bits concatenated with B bits by using B bits from the converted information produced by the conversion means and A bits of an offset portion of physical address carried by the external address bus, said invalidation control means supplying an address having A bits concatenated with B bits to a tag portion of a cache, and said invalidation control means causing a valid information stored in the memory to become inactive in order to invalidate the content of said memory corresponding to the address provided by A bits concatenated with B bits which are supplied by said invalidation control means.

A memory control system comprising:

• a first memory to be accessed by a logical address including A bits concatenated with B bits;
• a second memory which is accessed by another address, said another address being composed of A bits, and wherein said second memory comprises 2.sup.B regions in said another address designated by A bits;
• means for writing a part of a physical address into an address of said first memory designated by A bits concatenated with B bits and writing the same physical address as written in the first memory in at least one of said 2.sup.B regions in said address designated by A bits in the second memory during a registration operation;
• comparison means for, when external information including said A bits and bits representing the physical address is provided to the second memory, accessing the second memory by using A bits of the external information, reading the content of said address designated by A bits and comparing the content of the respective 2.sup.B regions with said part of the physical address of said external information, and detecting the region in which the part of the physical address stored in the region accords with the part of the physical address of the external information during an address monitor operation;
• and
• invalidating means for producing B bits by encoding the result of said comparing means, combining the B bits with the A bits to provide A bits concatenated with B bits, thereby accessing said first memory and invalidating information stored in said first memory by using A bits concatenated with B bits when an external CPU changes the content in a main memory which corresponds to the physical address.

A memory control system comprising:

• a first memory to be accessed by A bits concatenated with B bits, and wherein said first memory has information written therein;
• and an address monitor means comprising:
• a second memory for storing said information in one of 2.sup.B regions of an address of said second memory, said region being determined by information corresponding to said B bits and said address being accessed by said A bits, and
• means for reproducing said B bits based on region in which external information coincides with said information in said second memory, thereby producing A bits concatenated with B bits in said first memory.