Electronic apparatus featuring a plurality of selectable memories
AssigneeCanon Kabushiki Kaisha
InventorShigemitsu Tasaki
Life of this patent
Estimating the term…
Abstract
An electronic apparatus having read-only memories (ROMs), wherein a second ROM having a region capable of being read with addresses common to a part of an address region of a first ROM can be connected. Reading from addresses included within the address region of the first ROM is performed from the second ROM when the addresses are also included within the address region of the second ROM, and from the first ROM for other cases. Furthermore, the first ROM can be replaced with a third ROM, to which addresses not overlapped with those of the second ROM are assigned.
Claims5
An electronic apparatus comprising:
- a first read-only memory fixedly connected to said apparatus for storing information and having a plurality of address regions in a single chip structure;
- a second read-only memory detachably connected to said apparatus for storing information and having an address region in common with one of the plurality of address regions in said first read-only memory;
- address decoding means for decoding a received address and outputting a select signal on one of a first and a second signal line, wherein said address decoding means outputs the select signal on the first signal line when the received address is in the common address region and outputs the select signal on the second signal line when the received address is in the plurality of address regions other than the common address region, and wherein the second signal line is electrically connected to said first read-only memory;
- manual switch means for electrically connecting the first signal line with one of said first and second read-only memories, alternatively;
- and
- reading means for reading out information from one of said first and second read-only memories selected by the select signal.
An electronic apparatus comprising:
- first connection means for fixedly connecting to said apparatus a first read-only memory for storing information and having a plurality of address regions in a single chip structure;
- second connection means for detachably connecting to said apparatus a second read-only memory for storing information and having an address region in common with one of the plurality of address regions in said first read-only memory;
- address decoding means for decoding a received address and outputting a select signal on one of a first and a second signal line, wherein said address decoding means outputs the select signal on the first signal line when the received address is in the common address region and outputs the select signal on the second signal line when the received address is in the plurality of address regions other than the common address region, and wherein the second signal line is electrically connected to said first read-only memory;
- manual switch means for electrically connecting the first signal line with one of said first and second read-only memories, alternatively;
- and
- control means for controlling said apparatus so as to read information from the memory supplied with the select signal via one of said first and second connection means.
A method for reading out information from first and second read-only memories, the first read-only memory, fixedly connected to an electronic apparatus, having a plurality of address regions in a single chip structure, and the second read-only memory, detachably connected to the electronic apparatus, having an address region in common with one of the plurality of address regions in the first read-only memory, said method comprising the steps of:
- attaching the second read-only memory to the apparatus;
- electrically connecting a first output line of an address decoder with the second read-only memory by means of a manual switch, wherein a second output line of the decoder is electrically connected with the first read-only memory;
- requesting to read out information from a desired address;
- decoding the desired address and outputting a select signal on one of the first and the second output line by means of the address decoder, wherein the address decoder outputs the select signal on the first output line when the desired address is in the common address region and outputs the select signal on the second output line when the desired address is in the plurality of address regions other than the common address region;
- and
- reading out information stored in the desired address of the read-only memory supplied with the select signal.
Dependencies are inferred from the claim text.