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AssigneeUnisys Corporation
InventorsKhorvash Sefidvash, Charles E. Nogales
Estimating the term…
A buffer memory holding blocks of data received from a main host computer has dedicated portions for data destined for different sets of sender-receiver units. Each sender-receiver unit has a channel bus path to the buffer memory and each channel bus is monitored by an on-the-fly integrity checking circuit. A control processor and associated bus arbitration logic provide signals to a multiplexer so as to allocate equal access periods to each channel bus for connection to the buffer memory. A data feeder control on each transfer channel senses the availability of data block words in each dedicated segment of the buffer memory so that partial transfers of word blocks may occur on minor cycles with subsequent completion of the blocks of data words on a major transfer cycle.
A data transfer system for conveying different length blocks of data bytes between a plurality of host computers and a plurality of peripheral devices said data blocks having different byte lengths and a Block Error Detection Code for each block, said system comprising:
In a computer network wherein a host processor generates Write/Read commands to initiate a major cycle for the transfer of "N" blocks of data between a host processor and a specific peripheral device, a multiple path integrity checking data transfer system comprising:
Dependencies are inferred from the claim text.