Data compression/encryption processing apparatus

A data processing apparatus comprising:

• a block processing section for dividing message data into a plurality of blocks, so as to obtain a plurality of data blocks;
• and
• a plurality of data conversion processing sections which are provided in correspondence to the data blocks and each of which stores a plurality of data conversion algorithms therein, a first one of said data conversion processing sections selecting one of the data conversion algorithms in response to an initial selection control signal and each of remaining ones of said data conversion processing sections selection one of the data conversion algorithms in response to a selection control signal supplied from a preceding data conversion processing section, each of said data conversion processing sections performing data conversion processing with respect to the corresponding data block on the basis of the selected data conversion algorithm and generating a selection control signal used for processing a next data block on the basis of the data conversion processing, wherein each of said data conversion processing sections includes an input processor, an algorithm operation processor, and an algorithm selection controller;
• processing data is transferred from each of said data conversion processing sections to an immediately succeeding data conversion processing section;
• each input processor adds processing data of a preceding data conversion processing section to its corresponding data block;
• each algorithm operation processor has a plurality of function algorithms previously stored therein, and operates on the function algorithms in response to the selection control signal to thereby generate each of said data conversion algorithms, and performs data conversion processing with respect to the data obtained by the input processor on the basis of the data conversion algorithms;
• each algorithm selection controller generates one of said selection control signals on the basis of a processing result of the algorithm operation processor, said selection control signal controlling selection of a data conversion algorithm to be executed by an algorithm operation processor of a succeeding data conversion processing section;
• and
• each algorithm selection controller controls the selection of the data conversion algorithm to be executed by the algorithm operation processor of the succeeding data conversion processing section, such that temporal changes in said data conversion algorithm form a finite-state discrete-time Markovian process.