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US 5,517,584 AGranted
Method and apparatus for high-speed implementation of scaling, dithering, and data remapping operations with a single processor
AssigneeUnisys Corporation
InventorKevin F. Jennings
Life of this patent
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Abstract
An image processing hardware element that may be used to implement any number of data manipulation methods. The hardware element may be dedicated to the selected manipulation method such that maximum performance may be attained. The hardware element may be programmed to implement a particular manipulation method by simply down loading new values into the hardware element.
Claims21
In an image processing system having a stream of input data comprising a plurality of data elements and a receiving user, the image processing system being capable of performing at least one data manipulation method on the stream of input data and provide the result to the receiving user, the improvement comprising:
- a. a first LUT element having an input and an output, said input for receiving the stream of input data, said first LUT element performing a predetermined function on said the stream of input data and providing a result to said output;
- b. a second LUT element having an input and an output, said input for receiving the stream of input data, said second LUT element performing a predetermined function on the stream of input data and providing a result to said output;
- c. an input data select block coupled to said input of said first LUT element and to said input of said second LUT element for routing the stream of input data to said input of said first LUT element and to said input of said second LUT element;
- d. a packer coupled to said first LUT element and to said second LUT element for selecting a predetermined portion of said result provided by said first LUT element and for selecting a predetermined portion of said result provided by said second LUT element;
- e. a post processor coupled to said packer for collecting said selected portion of said result provided by said first LUT element and for collecting said selected portion of said result provided by said second LUT element and providing a result to the receiving users;
- and
- f. a control circuit for providing an index field to said input of said first LIFE element and to said input of said second LUT element.
4 more elements
An image processing apparatus having a stream of input image data comprising a plurality of data elements and a receiving user, comprising:
- a. first storage means having an input and an output wherein said input of said first storage means for receiving input data, said first storage means for performing a predetermined function on said input data via a first look-up method, and providing a result to said output;
- b. second storage means having an input and an output wherein said input of said second storage means for receiving input data, said second storage means for performing a predetermined function on said input data via a second look up method, and providing a result to said output;
- c. routing means coupled to said input of said first storage means and to said input of said second storage means for routing the stream of input image data to said input of said first storage means and to said input of said second storage means;
- d. selecting means coupled to said first storage means and to said second storage means for selecting a predetermined portion of said result provided by said first storage means and for selecting a predetermined portion of said result provided by said second storage means;
- and
- e. collecting means coupled to said selecting means for collecting said selected portion of said result provided by said first storage means and for collecting said selected portion of said result provided by said second storage means and providing a result to the receiving users.
3 more elements
A method for performing a predetermined one of a plurality of data manipulation algorithms on a plurality of input data elements resulting in a plurality of output data elements, comprising:
- a. providing a first memory element having an address input and a data output, the first memory element having a plurality of contents wherein a particular one of the plurality of contents is provided to the output when an address is provided on the address input;
- b. providing a second memory element having an address input and a data output, the second memory element having a plurality of contents wherein a particular one of the plurality of contents is provided to the output when an address is provided on the address input;
- c. providing an index field to the address input of the first memory element and to the address input of the second memory element;
- d. providing an adder wherein the adder is coupled to the output of the first memory element and is further coupled to the output of the second memory element;
- e. providing a first one of the plurality of input data elements to the address input of the first memory element;
- f. providing a second one of the plurality of input data elements to the address input of the second memory element;
- g. programming the contents of the first memory element and the second memory element and further programming the index field to perform the predetermined one of the plurality of data manipulation algorithms;
- h. adding a predetermined portion of the particular one of the plurality of contents that is provided to the output of the first memory element and a predetermined portion of the particular one of the plurality of contents that is provided to the output of the second memory element resulting in one of the plurality of output data elements;
- and
- i. repeating steps (e)-(h) until all of the plurality of input data elements have processed.
7 more elements
Dependencies are inferred from the claim text.