Circuit device for controlling circuit components connected in series or in a matrix-like network

#The present invention relates to an electronic circuit

#for controlling circuit components connected electrically in series or in a matrix-like network which is part of a shift register.

#Controlling such serially connected or matrix connected circuit components is necessary for addressing the row and column conductors of a liquid crystal display screen. Such active-matrix liquid crystal-display screens (so-called AM-LCDs) are to be used increasingly in the future to replace display devices with cathode ray tubes in television and data processing, since they have a number of advantages: reduced weight, flat structure, no distortion of the picture produced, low control voltages, reduced power consumption, possible use as a light valve in a projector, high resolution, no generated X-radiation as in the case of a cathode ray tube, no strong magnetic and electric fields originating from the display device and economical manufacture, which is particularly suitable for large screen applications.

#The objects, features and advantages of the invention will now be illustrated by the following preferred embodiments in the detailed description, reference being made to the drawing in which:

#FIG. 1 is a circuit diagram of a first embodiment of the circuit device according to the invention for the nth stage of a dynamic shift register;

#FIG. 2 is a pulse diagram for the circuit device of FIG. 1 at a shift frequency of 10 MHz;

#FIG. 1 shows one embodiment of a circuit arrangement according to the invention as an nth stage of a dynamic shift register. The shift register is controlled by four periodic signals .PHI..sub.1, .PHI..sub.2, .PHI..sub.3 and .PHI..sub.4, which are applied to the terminals PHI1-PHI4 and those form is sketched at the left hand side of the terminals PHI1-PHI4. The periodic signals .PHI..sub.1, .PHI..sub.2, .PHI..sub.3 and .PHI..sub.4 are phase shifted 90.degree. relative to each other. The periodic signal pairs .PHI..sub.1 /.PHI..sub.3 and .PHI..sub.2 /.PHI..sub.4 are not overlapped so that no cross-current occurs in the circuit device. Furthermore the circuit device is provided with a constant supply voltage U.sub.dd.

#The shift register according to FIG. 1 is divided into three partial stages: an inverter stage 10, a bootstrap-capacitor charging and discharging stage 11 and an output stage 12. The inverter stage 10 comprises two transistors T.sub.n1, T.sub.n2 and the capacitor C.sub.n1. The transistor T.sub.n2 charges the capacitor C.sub.n1 periodically during the high level of the periodic signal .PHI..sub.3. By selecting the periodic voltage U.sub..PHI.3 >U.sub.dd +U.sub.th, where U.sub.th is the threshold voltage of the transistors, the transistor T.sub.n2 operates very quickly to the voltage U.sub.dd. The discharging of the capacitor C.sub.n1 in the "initial or starting region" and charges the capacitor C.sub.n1 occurs through the transistor T.sub.n1, when it is switched by an input signal E.sub.n. From the pulse diagram of FIG. 2 it is apparent that the signals .PHI..sub.3 and E.sub.n never have a high level simultaneously to guarantee that T.sub.n1 and T.sub.n2 are never simultaneously conducting and as a result only very small cross-currents, namely the blocking current of the field effect transistors, flows. In the shift register circuit used currently with field effect transistors of the n-MOS-enriched type, particularly those with two-phase pulses, the transistor T.sub.n2 is used as a load element. Furthermore gates and drains of the transistor T.sub.n2 are jointly connected to the pulse voltage so that the transistor T.sub.n2 is exclusively operated in the "saturated" condition. As a result the memory capacitor C.sub.n1 is charged only to a voltage U.sub.C" =U.sub..PHI.2 -U.sub.th. Which also depends on the threshold voltage U.sub.th Furthermore the low-output level of the conventional inverter circuit is determined by the ratio of the quotient of the channel length and channel width of the load and switching transistors and thus is always greater than 0 V. In contrast the transistors T.sub.n1 and T.sub.n2 of the circuit shown in FIG. 1 only have the function of a switch for discharging and/or charging the memory capacitor C.sub.n1. The inverter output voltage U.sub.Cn does not depend on the geometry and the threshold voltage U.sub.th of the transistors T.sub.n1 and T.sub.n2, when U.sub..PHI.1 >U.sub.dd +U.sub.th is chosen. Only the side steepness of the output pulse U.sub.Cn is influenced by the threshold voltage U.sub.th. The circuit reliability for subsequent shift register stages is thus substantially increased.

#The bootstrap capacitor charging and discharging stage 11 comprises only two transistors T.sub.n3 and T.sub.n4. The bootstrap capacitor C.sub.n8 is charged to a constant voltage U.sub.dd during a high level of the signal E.sub.n by the transistor T.sub.n4. This guarantees that the voltage U.sub.dd is at least about the periodic voltage U.sub..PHI.1 less than the threshold voltage U.sub.th and the channel width of the transistor T.sub.n4 is adjusted to the size of the capacitor C.sub.nB. The bootstrap capacitor C.sub.nB is again discharged by the transistor T.sub.n3, which is controlled by the periodic signal .PHI..sub.3 . Thus it is guaranteed that both transistors T.sub.n3 and T.sub.n4 are not simultaneously conducting.