Synchronous type semiconductor memory device operating in synchronization with an external clock signal

A synchronous type semiconductor memory device taking in an external control signal in synchronization with an externally and periodically applied clock signal, comprising:

• a plurality of memory cells;
• an internal data line for transferring data to and from a selected memory cell;
• and
• precharge means activated for a predetermined time period in synchronization with the clock signal, for precharging said internal data line to a predetermined potential.

A synchronous type semiconductor memory device taking in an external control signal in synchronization with an externally and periodically applied clock signal, comprising:

• a plurality of memory cells arranged in rows and columns;
• means for storing a wrap length data indicating a number of data successively read out or written into a synchronization with the clock signal;
• an internal data line for transferring data to and from a selected memory cell;
• precharge means for precharging said internal data line to a predetermined potential;
• counting means responsive to a column selection start instructing signal for counting the clock signal;
• and
• precharge control means responsive to the column selection start instructing signal for disabling said precharge means, and for enabling said precharge means to precharge said internal data line to said predetermined potential when a count by said counting means becomes equal to the number indicated by said wrap length data.

A synchronous type semiconductor memory device taking in an external control signal in synchronization with an externally and periodically applied clock signal, comprising:

• a plurality of memory cells arranged in rows and columns;
• means for generating an internal mask signal in an active state inhibiting writing of data into a selected memory cell for each applied write data in a data write mode of operation;
• determination means receiving an external write mask signal applied with said each applied write data and for determine whether the external write mask signal designates an inhibition of writing of an associated applied write data in the date write mode of operation;
• and
• write control means responsive to said determination means determining that said external write mask signal designates permission of writing of the associated applied write data, for deactivating said internal mask signal to permit the writing of data into the selected memory cell.