Semiconductor memory device having refresh circuits

A semiconductor memory device including dynamic memory cells for which refresh operation is required,

• wherein one fundamental cycle consists of a normal operation for carrying out writing or reading into or from said memory cells and a refresh operation,
• said semiconductor memory device comprising:
• a refresh signal generating circuit supplied with a clock signal to generate a refresh signal indicating start of refresh;
• a count signal generating circuit supplied with said clock signal to generate a count signal required for selection of a memory cell to be refreshed;
• a refresh counter circuit supplied with said refresh signal outputted from said refresh signal generating circuit and said count signal outputted from said count signal generating circuit to select a word line and a bit line to which a memory cell to be refreshed is connected;
• and
• a precharge circuit supplied with said refresh signal outputted from said refresh signal generating circuit to carry out precharge of said bit line for refresh.