US 5,517,451 AGranted

Semiconductor memory device and memory initializing method

AssigneeTexas Instruments Incorporated

InventorKiyotaka Okuzawa

Life of this patent

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Abstract

A semiconductor memory device and an initialization method therefor, wherein writing of the initialization data into memory cells of the semiconductor memory device can be performed in a simple way in a short period of time. When initialization is performed, a high (H) level initialization mode signal DFT is generated from initialization control unit 24. A sense amplifier driving circuit 20 sets a sense amplifier driving signal PC, NC to the high-impedance state, equalization control signal generating unit 22 maintains the equalization control signal .phi.E on the H-level, and bit line driving circuit 26 sets precharge feed line BLR on Vcc (H-level) or Vss low (L) level). In this way, in the memory cell array, the operation of sense amplifier SAi of each row stops, and transistors TR3, TR4, TR5 of precharge circuit PRi are ON, while voltage Vcc or Vss of precharge feed line BLR is fed to two bit lines BLi, BLi- through transistors TR1, TR2. In this state, the word line WLj of the assigned column is activated.

Claims10

Dependent claims

A semiconductor memory device comprising;

an array of memory cells arranged in a matrix of rows and columns of individual memory cells;
a pair of complementary bit lines for each of said rows of memory cells and connected to the same side of each of the memory cells included in a respective row;
a plurality of word lines corresponding to the columns of memory cells and arranged orthogonally with respect to the pairs of complementary bit lines for each of said rows of memory cells;
a plurality of cross points defined by the intersections formed between the orthogonally related word lines and pairs of complementary bit lines;
one-half of the columns of memory cells being connected at the respective cross points between one bit line of the pair of complementary bit lines and the word lines corresponding to said one-half of the columns of memory cells;
the other half of the columns of memory cells being connected at the respective cross points between the other bit line of the pair of complementary bit lines and the word lines corresponding to the said other half of the columns of memory cells;
said pairs of complementary bit lines for each of said rows of memory cells normally having complementary logic values in the performance of read and write operations of the semiconductor memory device;
initializing means operably connected to said pairs of complementary bit lines for establishing the same binary logic value at either the high level "1" or the low level "0" for both of the bit lines included in each of said pairs of complementary bit lines at the same time;
and
means for selecting at least one word line for writing the same binary logic value into each of the respective memory cells connected to both bit lines of the complementary bit line pair.

7 more elements

A method of initializing a semiconductor memory device to test for the stored information in the semiconductor memory device, said method comprising:

providing an array of memory cells arranged in a matrix of rows and columns of individual memory cells;
associating a pair of bit lines for each of the rows of memory cells and connected to a differential sense amplifier for the respective row of memory cells;
arranging one-half of the columns of memory cells connected at respective cross points between one bit line of the pair of bit lines and the word lines corresponding to said one-half of the columns of memory cells;
arranging the other half of the columns of memory cells connected at the respective cross points between the other bit line of the pair of bit lines and the word lines corresponding to the said other half of the columns of memory cells;
and
initializing the memory cells included in at least one row corresponding to a word line, the initializing of the memory cells including
setting each of the bit lines included in respective pairs of bit lines associated with the memory cells included in a row to substantially the same voltage level representative of one of two binary logic values as a high level "1" or a low level "0",
activating at least one word line of said plurality of word lines, and
writing data of the same logic value as set in the respective pairs of bit lines into each of the memory cells included in said at least one row simultaneously.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/186,186Filed 24 Jan 1994
Priority: JP 5-02733522 Jan 1993
Granted: 14 May 1996
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 11/4094
Read-write [R-W] circuits: bit-line management or control circuits
G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 7/20
Arrangements for writing information into, or reading information out from, a digital store: memory cell initialisation circuits, e.g. when…
G11C 11/4072
For memory cells of the field-effect type: circuits for initialization, powering up or down, clearing memory or presetting