Semiconductor memory device with redundancy circuit

A semiconductor memory device, comprising:

• a memory cell array including memory cells arranged in a plurality of subarrays which are each divided into a plurality of memory cell blocks;
• row selecting means for selecting rows of said memory cell array;
• column selecting means for selecting columns of said memory cell array;
• spare memory cells for replacing defective memory cells of said memory cell array;
• spare memory cell selecting means responsive to input addresses which correspond to defective memory cells of said memory cell array for selecting said spare memory cells and for outputting a signal to said column selecting means for inhibiting said column selecting means from selecting columns of said memory cell array;
• selecting control means for supplying a row address to control said row selecting means to simultaneously activate at least two memory cell blocks in each of said subarrays;
• and
• changing means for selectively changing an assignment of the row address supplied from said selecting control means to thereby change which memory cell blocks are simultaneously activated by said row selecting means.

A semiconductor memory device, comprising:

• a memory cell array including rows and columns of memory cells organized into memory cell blocks;
• row selecting means for selecting rows of memory cells of said memory cell array;
• column selecting means for selecting columns of memory cells of said memory cell array;
• spare memory cells for replacing defective memory cells of said memory cell array;
• spare memory cell selecting means responsive to input addresses which correspond to defective memory cells of said memory cell array for selecting said spare memory cells and for outputting a signal to said column selecting means for inhibiting said column selecting means from selecting columns of memory cells of said memory cell array;
• and
• changing means for selectively changing an assignment of a row address supplied to said row selecting means, wherein said row selecting means is responsive to a row address supplied thereto for simultaneously activating at least two memory cell blocks and the changing of the row address assignment by said changing means changes which of said memory cell blocks are simultaneously activated by said row selecting means.

A semiconductor memory device, comprising:

• a memory cell array including memory cells arranged in a plurality of subarrays which are each divided into a plurality of memory cell blocks;
• row selecting means for selecting rows of said memory cell array;
• column selecting means for selecting columns of said memory cell array;
• spare memory cells for replacing defective memory cells of said memory cell array;
• spare memory cell selecting means responsive to input addresses which correspond to defective memory cells of said memory cell array for selecting said spare memory cells and for outputting a signal to said column selecting means for inhibiting said column selecting means from selecting columns of said memory cell array;
• and
• changing means for selectively changing an assignment of a row address supplied to said row selecting means, wherein said row selecting means is responsive to a row address supplied thereto for simultaneously activating at least two memory cell blocks in each of said subarrays and the changing of the row address assignment by said changing means changes which of said memory cell blocks are simultaneously activated by said row selecting means.

A semiconductor memory device, comprising:

• a memory cell array including rows and columns of memory cells organized into memory cell blocks;
• a row decoder for decoding a row address to select rows of said memory cell array;
• a column decoder for decoding a column address to select columns of said memory cell array;
• spare memory cells for replacing defective memory cells of said memory cell array;
• a spare column decoder, programmed with defective column addresses of said memory cell blocks, for selecting spare memory cells and inhibiting said column decoder from selecting columns of said memory cell array when the decoded column address corresponds to one of the defective column addresses;
• a block selecting signal generator for generating a block selecting signal in response to the row address, said block selecting signal generator supplying the block selecting signal to said row decoder such that a plurality of memory cell blocks are simultaneously selected;
• and
• an address assignment changing circuit for selectively changing an assignment of the row address to change the block selecting signal output by said block selecting signal generator.

A semiconductor memory device, comprising:

• a memory cell array including memory cells arranged in a plurality of subarrays which are each divided into a plurality of memory cell blocks;
• a row decoder for decoding a row address to select rows of said memory cell array;
• a column decoder for decoding a column address to select columns of said memory cell array;
• spare memory cells for replacing defective memory cells of said memory cell array;
• a spare column decoder, programmed with defective column addresses of said memory cell blocks, for selecting spare memory cells and inhibiting said column decoder from selecting columns of said memory cell array when the decoded column address corresponds to one of the defective column addresses;
• a block selecting signal generator for generating a block selecting signal in response to the row address, said block selection signal generator supplying the block selection signal to said row decoder such that a plurality of memory cell blocks in each subarray are simultaneously selected;
• and
• an address assignment changing circuit for selectively changing an assignment of the row address to change the block selecting signal output by said block selection signal generator.

A semiconductor memory device, comprising:

• a memory cell array including rows and columns of memory cells organized into memory cell blocks;
• a row decoder for decoding a row address to select rows of memory cells of said memory cell array;
• a column decoder for decoding a column address to select columns of memory cells of said memory cell array;
• spare memory cells for replacing defective memory cells of said memory cell array;
• a spare column decoder, programmed with defective column addresses of said memory cell blocks, for selecting spare memory cells and inhibiting said column decoder from selecting columns of memory cells of said memory cell array when the decoded column address corresponds to one of the defective column addresses;
• and
• an address assignment changing circuit for selectively changing an assignment of the row address in order to change which memory cell blocks are simultaneously activated by said row decoder.

A semiconductor memory device, comprising:

• a memory cell array including memory cells arranged in a plurality of subarrays which are each divided into a plurality of memory cell blocks;
• a row decoder for decoding a row address to select rows of said memory cell array;
• a column decoder for decoding a column address to select columns of said memory cell array;
• spare memory cells for replacing defective memory cells of said memory cell array;
• a spare column decoder, programmed with defective column addresses of said memory cell blocks, for selecting spare memory cells and inhibiting said column decoder from selecting columns of said memory cell array when the decoded column address corresponds to one of the defective column addresses;
• and
• an address assignment changing circuit for selectively changing an assignment of the row address to change which memory cell blocks are simultaneously activated by said row decoder.