Bias circuit for virtual ground non-volatile memory array with bank selector

A bias circuit for a virtual ground non-volatile memory array with bank selector, wherein said memory array includes a plurality of banks, each bank including a memory sub-array consisting of a plurality of columns and rows of memory cells, a plurality of bank selectors, and a plurality of alternately arranged data sense bit lines and virtual ground bit lines connected between said bank selectors, said bias circuit comprising:

• a global bias circuitry connected to all of said data sense bit lines and said virtual ground bit lines for providing a first predetermined bias voltage to all said data sense bit lines and said virtual ground bit lines:
• a local bias circuitry;
• and
• a column multiplexer connected between said banks and said local bias circuitry, said column multiplexer, according to the memory cell selected to be accessed, selecting a corresponding data sense bit line as a selected data sense bit line, and selecting one of two of said virtual ground bit lines which are respectively adjacent to two sides of said selected data sense bit line as a selected virtual ground bit line, and the other as a selected local isolation bit line, and then said column multiplexer connecting said selected data sense bit line, said selected virtual ground bit line and said selected local isolation bit line to said local bias circuitry, and isolating the rest of said data sense bit lines and virtual ground bit lines from said local bias circuitry;
• wherein said local bias circuitry provides a second predetermined bias voltage to said selected data sense bit line, a third predetermined bias voltage to said selected local isolation bit line, and a reference voltage to said selected virtual ground bit line.