Random access memory and an improved bus arrangement therefor
AssigneeInternational Business Machines Corporation
InventorsToshiaki Kirihata, Yohji Watanabe, Hing Wong
Life of this patent
Estimating the term…
Abstract
The present invention is a bus arrangement for a wide I/O Random Access Memory (RAM). The bus arrangement includes a global address bus which drives row/column predecoders and redundancy comparators placed at each edge of the memory array. Two banks of sixteen data I/O (DQs), one bank for each half chip, are placed at either end of the chip providing up to a .times.32 I/O organization. The main Read/Write Data lines (RWD) are more densely populated near the chip edge than the chip center to provide .times.4 and .times.8 options, as well. A local address bus is in the open space between the RWDs to redrive the global address lines at their quarter points.
Claims11
A Random Access Memory (RAM) comprising:
- a memory array, said memory array being divided into two halves, each said half including a plurality of memory units, each said unit including a plurality of memory cells;
- each said half having a global bus along one side;
- a pair of Data I/O banks (DQ), said pair of DQs being located at opposite ends of said RAM between said global busses;
- and,
- a local bus between said global busses.
Dependencies are inferred from the claim text.