Content addressable memory circuitry and method of operation
AssigneeInternational Business Machines Corporation
InventorsCarl D. Dietz, Kathryn J. Hoover
Life of this patent
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Abstract
Content addressable memory circuitry and a method of operation are provided. First information is stored. A logic state of a first match line is selectively modified in response to a comparison between the first information and second information. Also, third information is stored. A logic state of a second match line is selectively modified in response to a comparison between the third information and fourth information. A logic state of the second match line is selectively modified in response to the logic state of the first match line.
Claims21
Content addressable memory circuitry, comprising:
- first circuitry for storing first information and selectively modifying a logic state of a first match line in response to a comparison between said first information and second information;
- second circuitry for storing third information and selectively modifying a logic state of a second match line in response to a comparison between said third information and fourth information;
- and
- third circuitry for selectively modifying said logic state of said second match line in response to said logic state of said first match line.
A method of operating content addressable memory circuitry, comprising the steps of:
- storing first information;
- selectively modifying a logic state of a first match line in response to a comparison between said first information and second information;
- storing third information;
- selectively modifying a logic state of a second match line in response to a comparison between said third information and fourth information;
- and
- selectively modifying said logic state of said second match line in response to said logic state of said first match line.
Dependencies are inferred from the claim text.