Fast multiply-add instruction sequence in a pipeline floating-point processor

A floating point processor comprising:

• a multiply section having:
• a first input register and a second input register for intermediately storing first and second operands,
• a multiplier coupled to the first and second input registers for performing a multiplication of the first and second operands,
• adder output registers coupled to the multiplier for intermediately storing partial sums of the multiplication,
• a first adder coupled to the adder output registers for performing an addition of the partial sums, and
• a first normalizer connected to the first adder for normalizing a result of the addition of the partial sums;
• and
• an add section having:
• a third input register and a fourth input register for intermediately storing the first and second operands,
• a first aligner connected to said third input register for aligning the first operand,
• a first left shifter connected to the first aligner,
• a second aligner connected to said fourth input register for aligning the second operand,
• a second left shifter connected to the second aligner,
• a true/complement unit coupled to the first left shifter for operand true/complement building,
• a first zero setter connected to the true/complement unit,
• a first adder input register coupled to the first zero setter for intermediately storing an output of the first zero setter,
• a second zero setter connected to the second left shifter,
• a second adder input register coupled to the second zero setter for intermediately storing an output of the second zero setter,
• a second adder coupled to the first and second adder input registers for adding outputs of the first and second adder input registers,
• a second normalizer connected to said second adder for normalizing an output of said second adder;
• and
• a feedback path connecting said first normalizer to each of said first and second aligners.