US 5,517,432 A · Finite state machine transition analyzer

Abstract

A state machine synthesis tool, a state table script generator, a state table extraction tool, a simulation driver, a simulator, and an interactive reporter, are provided to verify the design and implementation of finite state machines (FSMs). The synthesis tool takes a formal specification of a logic circuit where FSMs are embedded as input, and generates a gate level specification of the logic circuit. The state table script generator takes the same formal specification of the logic circuit as input, and generates state table extraction command files for the FSMs. The state table extraction tool takes the gate level specification of the logic circuit and the state table extraction command files of the FSMs as inputs, and generates state tables for the FSMs. The simulation driver takes the state tables of the FSMs as inputs, and in cooperation with the simulator, which takes the gate level specification of the logic circuit and a number of functional vectors as inputs, simulates the logic circuit and generates simulation results of the FSMs. Finally, the interactive reporter takes the simulation results of the FSMs, the state tables and user commands as inputs, and generates the analysis results that allow verification of the design and implementation of the FSMs.

Claims18

Dependent claims

In a computer system comprising a formal specification of a logic circuit having at least one finite state machine (FSM) and at least one set of functional vectors for simulating the logic circuit, an apparatus for analyzing and verifying said at least one FSM's design and implementation, said apparatus comprising:

a) synthesis means for generating a gate level specification of said logic circuit in response to said formal specification of said logic circuit;
b) state table generation means comprising:
b.1) command script generation means for generating at least one state table extraction command script file for said at least one FSM in response to said formal specification of said logic circuit:
and
b.2) state table extraction means for generating said at least one state table for said at least one FSM in response to said gate level specification of said logic circuit and said at least one state table extraction command script file;
c) simulation means for simulating and generating simulation results of said at least one FSM in response to said gate level specification of said logic circuit, said at least one state table for said at least one FSM, and said at least one set of functional vectors;
and
d) reporting means for generating analysis reports in response to said simulation results of said at least one FSM and user inputs.

5 more elements

In a computer system comprising a formal specification of a logic circuit having at least one finite state machine (FSM) and at least one set of functional vectors for simulating the logic circuit, a method for analyzing and verifying said at least one FSM's design and implementation, said method comprising the steps of:

a) generating a gate level specification of said logic circuit in response to said formal specification of said logic circuit;
b) generating a state table for each of said at least one FSM in response to said formal specification of said logic circuit;
c) simulating and generating simulation results of said at least one FSM in response to said gate level specification of said logic circuit, said at least one state table for said at least one FSM, and said at least one set of functional vectors;
and
d) generating analysis reports by the following steps:
d.1) interpreting user commands;
d.2) loading said at least one state table and simulation results for said at least one FSM responsive to said user commands;
d.3) storing said loaded at least one state table and said simulation results;
and
d.4) performing a plurality of reporting and related functions responsive to said user commands.

7 more elements

Dependencies are inferred from the claim text.

Finite state machine transition analyzer

Life of this patent

Finite state machine transition analyzer

Life of this patent

Abstract

Claims18